BCM1250/BCM1125/BCM1125H
Bits
Name
Default
6:0
tx_wr_thrsh
7
reserved
14:8
tx_rd_thrsh
15
reserved
21:16
tx_rl_thrsh
23:22
reserved
29:24
reserved
31:30
reserved
37:32
rx_rd_thrsh
39:38
reserved
45:40
rx_rl_thrsh
55:46
reserved
61:56
enc_fc_thrsh
63:62
reserved
Page
306
Section 9: Ethernet MACs
Table 179: MAC FIFO Threshold Registers
mac_thrsh_cfg_0 - 00_1006_4108
mac_thrsh_cfg_1 - 00_1006_5108
mac_thrsh_cfg_2 - 00_1006_6108
This register is used in both Ethernet and Packet FIFO modes
7'b0
Transmit FIFO write threshold. Sets the number of free 64 bit entries the transmit FIFO
must have before it signals that space is available. For DMA operation this field must be
set to 4 or 8 entries depending on the state of the tbx_en bit in the dma_config0 register.
See
Section: "Transmitter Configuration" on page
1'b0
Reserved
7'b0
Transmit FIFO read threshold. Sets the number of valid 64 bit entries the transmit FIFO
must hold before the MAC will start transmitting the packet. See
Configuration" on page
Note that the tx_wr_thrsh + tx_rd_thrsh must be less than the size of the fifo or the
transmitter behaviour is UNPREDICTABLE (tx_wr_thrsh + tx_rd_thrsh <= 32 for parts
with System Revision of 1, tx_wr_thrsh + tx_rd_thrsh <=128 for parts with revision
greater than 2).
1'b0
Reserved
6'b0
Transmit FIFO release count. This sets the number of 64 bit FIFO entries that will be
held in the FIFO when the MAC is configured to hold the start of packets. See the
tx_hold_sop_en bit in the mac_cfg register. See
Configuration" on page
2'b0
Reserved
6'b0
Reserved
2'b0
Reserved
6'b0
Receive read threshold. This field sets the number of entries that must be in the receive
FIFO for it to indicate data is available to be read. For DMA operation this field must be
set to 4 entries. See
2'b0
Reserved
6'b0
Receive release threshold. This field sets the number of FIFO entries that must be written
at the start of a packet before any of the data is made available for reading. The data is
also made available if the packet ends before the threshold is reached. See
Section: "Receiver Configuration" on page
This field must be greater than 2. If it is zero the MAC receive behavior will be
UNPREDICTABLE.
10'b0
Reserved
6'h4
In encoded Packt Fifo modes link level flow control will be requested when the number
of free doublewords in the receive fifo falls below this threshold.
2'b0
Reserved
B r oadco m C orp or ati on
Description
272.
272.
Section: "Receiver Configuration" on page 275
275.
User Manual
272.
Section: "Transmitter
Section: "Transmitter
Document
1250_1125-UM100CB-R
10/21/02
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