Broadcom BCM1250 User Manual page 478

BCM1250/BCM1125/BCM1125H
Name
duart_inport_chng_b
duart_inport_chng_debug
dma_config0_ser_0_rx
dma_config1_ser_0_rx
dma_dscr_base_ser_0_rx
dma_dscr_cnt_ser_0_rx
dma_cur_dscr_a_ser_0_rx
dma_cur_dscr_b_ser_0_rx
dma_cur_daddr_ser_0_rx
dma_config0_ser_0_tx
dma_config1_ser_0_tx
dma_dscr_base_ser_0_tx
dma_dscr_cnt_ser_0_tx
dma_cur_dscr_a_ser_0_tx
dma_cur_dscr_b_ser_0_tx
dma_cur_daddr_ser_0_tx
ser_mode_0
ser_minfrm_sz_0
ser_maxfrm_sz_0
ser_addr_mask_0
ser_usr0_addr_0
ser_usr1_addr_0
ser_usr2_addr_0
ser_usr3_addr_0
ser_cmd_0
ser_tx_rd_thrsh_0
ser_tx_wr_thrsh_0
ser_rx_rd_thrsh_0
ser_line_mode_0
ser_dma_enable_0
ser_status_0
ser_int_mask_0
dma_asic_addr_ser_0
ser_debug_status_0
ser_tx_byte_lo_0
Page 450 Section 16: Reference
Table 311: Internal Register Addresses by Function
Table/
Address
Page
209/331
00_1006_03E0
207/331
00_1006_03F0
91/163
00_1006_0400
92/164
00_1006_0408
93/166
00_1006_0410
95/166
00_1006_0418
96/167
00_1006_0420
97/167
00_1006_0428
98/167
00_1006_0430
91/163
00_1006_0480
92/164
00_1006_0488
93/166
00_1006_0490
95/166
00_1006_0498
96/167
00_1006_04A0
97/167
00_1006_04A8
98/167
00_1006_04B0
231/354
00_1006_0500
237/356
00_1006_0508
238/357
00_1006_0510
243/359
00_1006_0518
244/359
00_1006_0520
244/359
00_1006_0528
244/359
00_1006_0530
244/359
00_1006_0538
233/355
00_1006_0540
235/356
00_1006_0560
234/356
00_1006_0568
236/356
00_1006_0570
232/354
00_1006_0578
239/357
00_1006_0580
240/357
00_1006_0588
242/358
00_1006_0590
94/166
00_1006_0598
241/358
00_1006_05A8
246/360
00_1006_05C0
B r oadco m C orp or ati on
(Cont.)
Description
Input port change register for channel B (Read Only, read
clears channel B change state)
Alias of input port change register with no read side
effects. (Read Only)
Receive DMA control register.
Receive DMA control register.
Receive DMA descriptor base address.
Receive DMA descriptor count .
Receive DMA current descriptor A (Read Only).
Receive DMA current descriptor B (Read Only).
Receive DMA current descriptor address (Read Only).
Transmit DMA control register.
Transmit DMA control register.
Transmit DMA descriptor base address.
Transmit DMA descriptor count.
Transmit DMA current descriptor A (Read Only).
Transmit DMA current descriptor B (Read Only).
Transmit DMA current descriptor address (Read Only).
Mode select.
Min frame size.
Max frame size.
Address mask.
Match address 0.
Match address 1.
Match address 2.
Match address 3.
Command
Transmit FIFO read threshold.
Transmit FIFO write threshold.
Receive FIFO read threshold.
Line Interface configuration register.
DMA channel enable register.
Serial interface and DMA status (Read Only, read clears).
Interrupt mask.
ASIC mode address.
Serial interface and DMA status (Read Only, no side
effects).
Serial interface transmit byte count (low 16 bits).
User Manual
10/21/02
Document 1250_1125-UM100CB-R