Hypertransport Bounce Space; Performance Of The Pci And Hypertransport Interfaces - Broadcom BCM1250 User Manual

User Manual
10/21/02
Accesses from the ZBbus of one part to the F0_0000_0000 - F0_FFFF_FFFF region of the address map will
be sent over the HyperTransport fabric, accepted by the second part and direct mapped to a PCI access on
the second device.
There is a restriction on configuration accesses made from one part to another over the HyperTransport link.
Both reads and writes to the configuration registers must be 32 bit operations (a HyperTransport full unmasked
double-word), if bigger or smaller operations are performed reads will return UNPREDICTABLE values and
writes will leave the configuration register in an UNPREDICTABLE state.
Interface RevId 3 and later support the ActAsSlave function defined in the HyperTransport 1.03 specification,
which is of use in some double-hosted configurations.

HyperTransport Bounce Space

In a double-ended chain is used with a master host on one end and a slave on the other, peripherals will identify
the master device and direct all transactions to it. Anything that matches a memory address will be accepted
by the master. The slave has an identical memory map, so direct transactions will never reach it. The Bounce
space provides a way for the peripheral to bounce transactions to the slave via the master.
Any address received in the range F1_0000_0000 - FB_FFFF_FFFF will be sent back out on the
HyperTransport fabric with the address mapped to 01_0000_0000 - 0B_FFFF_FFFF (the top 4 bits are
cleared) and any address received in the range FC_0000_0000 - FC_FFFF_FFFF will be sent back out on the
HyperTransport fabric with the address mapped to 00_0000_0000 - 00_FFFF_FFFF (the top 8 bits are
cleared). This allows the device to access the memory space in the slave.
P
ERFORMANCE OF THE
The performance of the PCI and HyperTransport interfaces is strongly dependent on the size of the transfer.
The best case is when 32 byte cache blocks are moved. If smaller writes are done from the PCI or
HyperTransport into the part then the I/O bridge 0 has to read the cache block exclusive (to fetch any
modifications that may be in caches), modify it and write it back.
Writes from the ZBbus to either interface are always posted. Reads consist of two stages: the Read Request,
which is a non-posted request; and the Read-Data-Return (RDR) which is a response.
Document 1250_1125-UM100CB-R
PCI H
AND YPER
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
T I
RANSPORT NTERFACES
Section 8: PCI Bus and HyperTransport Fabric Page 213