Memory Map; Table 10: Overview Of Bcm1250 Physical Address Map - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
M M
EMORY AP
The memory map is designed to be usable in systems that only have 32 bit addressing and to provide
expansion for systems that can support the full 64 bit virtual address and 40 bit physical address of the SB-1
CPU. There are some additional restrictions that the MIPS architecture imposes:
• The reset vector of the CPU is to physical address 00_1FC0_0000.
• The exception vectors of the CPU are at physical address 00_0000_0000. (They may be offset from the
base by a multiple of 64K using the SB-1 MultiProcessor Vector extension in the CPU config register).
• The first 512 MB of memory is addressable uncached (and unmapped) in KSEG1 and is therefore a good
place for fixed address peripherals (they can be accessed without using any TLB entries).
In addition devices on the PCI need to be able to DMA into all of the physical memory (within the 32 bit PCI
address range) and be able to enable or disable endian swapping on each transaction (see
Policies" on page 201
memory map is given in
Base
00_0000_0000 00_0FFF_FFFF
00_1000_0000 00_1005_FFFF
00_1006_0000 00_3FFF_FFFF
00_4000_0000 00_5FFF_FFFF
00_6000_0000 00_7FFF_FFFF
00_8000_0000 00_9FFF_FFFF
00_A000_0000 00_BFFF_FFFF
00_C000_0000 00_CFFF_FFFF
00_D000_0000 00_D7FF_FFFF
00_D800_0000 00_D92F_FFFF
00_DC00_0000 00_DDFF_FFFF
00_DE00_0000 00_DFFF_FFFF
00_E000_0000 00_F7FF_FFFF
00_F800_0000 00_F92F_FFFF
00_FC00_0000 00_FDFF_FFFF
00_FE00_0000 00_FFFF_FFFF
01_0000_0000 7F_FFFF_FFFF
80_0000_0000 F7_FFFF_FFFF
F8_0000_0000 F8_FFFF_FFFF
F9_0000_0000 F9_FFFF_FFFF
FA_0000_0000 FC_FFFF_FFFF
FD_0000_0000 FF_FFFF_FFFF
Page 34 Section 3: System Overview
for a full discussion of PCI and HyperTransport endian policies). An overview of the
Table 10 and Figure 9

Table 10: Overview of BCM1250 Physical Address Map

Top
Memory controller.
System control and debug.
I/O system.
HyperTransport/PCI memory mapped I/O (32 bit addressing range)
Match byte lane endian policy.
HyperTransport/PCI memory mapped I/O (32 bit addressing range)
Match bit lane endian policy.
Memory controller.
Reserved
Memory controller.
L2 controller test.
HyperTransport special operations Match byte lane endian policy. Not on
BCM1125.
HyperTransport/PCI I/O space Match byte lane endian policy.
HyperTransport/PCI configuration space Match byte lane endian policy.
Reserved
HyperTransport special operations Match bit lane endian policy. Not on
BCM1125.
HyperTransport/PCI I/O space Match bit lane endian policy.
HyperTransport/PCI configuration space Match bit lane endian policy.
Memory controller expansion.
HyperTransport expansion (40 bit addressing range). Not on BCM1125.
PCI bus full access (match byte lane endian policy).
PCI bus full access (match bit lane endian policy).
Reserved
Reserved (Special HyperTransport range).
B r oadco m C orp or ati on
and a more detailed view is in
Owner
User Manual
10/21/02
Section: "Endian
Table 11 on page 36.
Document 1250_1125-UM100CB-R