Table 14: Manufacturing Information Register; Table 15: System Configuration Register - Broadcom BCM1250 User Manual

User Manual
10/21/02
Bits Name
63:0 mid
Bits Name
0 reserved
1 clk100_src
2 ldt_minrstcnt
3 ldt_bypass_pll
4 pci_test_mode
5 iob0_div
6 iob1_div
11:7 pll_div
12 ser0_enable
13 ser0_rstb_en
14 ser1_enable
15 ser1_rstb_en
16 pcmcia_enable
18:17 boot_mode
Document 1250_1125-UM100CB-R

Table 14: Manufacturing Information Register

system_manuf - 00_1003_8000 READ ONLY
Default
xx Manufacturing ID. Broadcom Use Only.

Table 15: System Configuration Register

system_cfg - 00_1002_0008
Default
ext Read Only, reflects the strap resistor on IO_AD[0].
ext Read Only, reflects the strap resistor on IO_AD[1] that selects the source for the
internal 100MHz clock and IO_CLK100 (if enabled).
ext Read Only, reflects the strap resistor on IO_AD[2]. Broadcom Use Only. This must
be zero for normal operation.
ext Read Only, reflects the strap resistor on IO_AD[3]. Broadcom Use Only. This must
be zero for normal operation.
ext Read Only, reflects the strap resistor on IO_AD[4]. Broadcom Use Only. This must
be zero for normal operation.
ext Read Only, reflects the strap resistor on IO_AD[5] that controls the clock divider
for I/O Bridge 0.
0: IOB0 runs at CPU clock/4, for use with fast CPU clocks.
1: IOB0 runs at CPU clock/3, for use with slow CPU clocks.
ext Read Only, reflects the strap resistor on IO_AD[6] that controls the clock divider
for I/O Bridge 1.
0: IOB1 runs at CPU clock/3, for use with fast CPU clocks.
1: IOB1 runs at CPU clock/2, for use with slow CPU clocks.
ext Read Only, reflects the strap resistors on generic IO_AD[11:7] that select the PLL
Divide ratio.
ext Read/Write. The default reflects the strap resistor on generic IO_AD[12] but this
bit can be written by software to change the setting.
0: Serial interface 0 is in asynchronous (uart) mode.
1: Serial interface 0 is in synchronous mode.
If this bit is changed by software it must also re-initialize the interface.
ext Read Only, reflects the strap resistor on generic IO_AD[13] that allocates GPIO[0]
pin to the synchronous serial interface.
ext Read/Write. The default reflects the strap resistor on generic IO_AD[14] but this
bit can be written by software to change the setting.
0: Serial interface 1 is in asynchronous (uart) mode.
1: Serial interface 1 is in synchronous mode.
If this bit is changed by software it must also re-initialize the interface.
ext Read Only, reflects the strap resistor on generic IO_AD[15] that allocates GPIO[1]
pin to the synchronous serial interface.
ext Read Only, reflects the strap resistor on generic IO_AD[16] that configured the
PCMCIA mode.
ext Reflects the strap resistor on generic IO_AD[18:17] that configured the boot mode.
00: 32 bit generic bus ROM (multiplexed)
01: 8 bit generic bus ROM (non-multiplexed)
10: SMBus EEPROM <= 16 kbit (read word protocol)
11: SMBus EEPROM > 16kbit (eeprom read word protocol).
Bit 17 is Read Only. Bit 18 can be changed by software to clear the SMBus boot
mode and allow general use of the SMBus 0 interface.
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Description
Description
Section 4: System Control and Debug Unit Page 43