Ethernet And Serial Dma Engines; Descriptor Count Watermarks - Broadcom BCM1250 User Manual

User Manual
10/21/02
E
THERNET AND
The Ethernet and serial DMA engines are identical except for using different per-packet options and status
flags. Each channel works as described above using either a ring or a chain. The DMA engines have the
restriction that neither the descriptors nor data buffers may be at an address serviced by I/O bridge 1, the
system behavior is UNDEFINED if this is violated. In practice this restriction just rules out DMA access from
the Ethernet or Serial DMA to the generic bus, since the other devices connected through I/O Bridge 1 are all
based on control registers and are unreasonable DMA targets.
behind I/O Bridge 1.
Both Ethernet and serial DMA controllers are connected to the ZBbus through I/O Bridge 1. In the direction
from the ZBbus to the devices there is a separate command queue for read and writes to peripheral registers
and response queue for data returning to descriptor or buffer DMA read requests. This ensures that the DMA
traffic is not blocked by requests to slow peripherals (such as a slow device on the generic bus). In the direction
towards the ZBbus it is important that if a status read reports completion of a command the response does not
pass that command, so read and write requests from the DMA engine and responses to register reads are held
in a single queue. Generic bus responses do not need this ordering and are given their own return queue.
Each channel has an interrupt associated with it. In the ethernet interface the status for the two receive and
two transmit DMA channels are combined into the mac_status register for the interface (see
Table 182 on page
ser_status register for each channel that can be read to determine the interrupt cause (see
Table 240 on page
D
ESCRIPTOR
The count of descriptors owned by the DMA controller is compared to two watermark registers. The high
watermark is set in the high_watermark field of the dma_config0 register, and the low watermark is set in the
low_watermark field. It is expected that the high watermark is programmed to a larger value than the low
watermark. The CPU can opt to be interrupted when the descriptor count falls below either (or both)
watermarks.
In a transmit engine setting the low watermark register to 1 and disabling the high watermark interrupt will give
an interrupt when all queued transmissions are complete.
In a receive engine the interface can be configured to use automatic flow-control. If this is enabled then when
the number of descriptors falls below the low watermark the interface will be signalled to use flow control to
apply back pressure, which will only be removed when sufficient descriptors have been supplied to push the
count above the high watermark. If the engine is configured to interrupt the CPU when the descriptor count
falls below the high watermark, software has a chance to allocate more receive descriptors before flow control
is asserted. If automatic flow control is enabled and the high watermark is smaller than the low watermark the
behavior of the engine is UNPREDICTABLE. The watermark based flow control will not activate until after
buffers have been added to the descriptor queue for the first time, so the link will not be jammed as the interface
comes out of reset.
Document 1250_1125-UM100CB-R
S DMA E
ERIAL
310). The serial interface transmit and receive channel status are combined into the
357). Reading the status will clear all bits in the status register and clear the interrupt.
C W
OUNT ATERMARKS
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
NGINES
Figure 5 on page 9 shows the devices that are
Section 7: DMA Page 157