Figure 21: Timing Relationships Set By Dlls - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
The drive position of the data relative to clock (t4 and t5) is controlled by the addr_skew parameter in the same
way as the address, except the data changes on both edges of the clock. The data transition point is thus offset
from both edges of the Mn_CLK by about 16% to 34% of the memory clock cycle time.
The third use of a DLL is to position the DQS strobe relative to the data during a write to the memory. The DQS
transition needs to be shifted to the center of the data valid window. This is done by shifting the DQS transition
from the data transition using a DLL controlled by the dqo_skew. The minimum delay between the data and
DQS (t6 in Figure
is about 34% of the cycle time with dqo_skew set to 4'b1111.
The second and third uses of the DLL interact to set the position of the DQS output relative to the clock. The
difference between the addr_skew and dqo_skew controls this delay (if they are set to the same value the
strobe will line up with the clock). The early DQS shown by t2 results from the addr_skew being set to
M=4'b1111 and dqo_skew to M=4'b0000, the difference in the delays will make the DQS precede the clock by
(35 - (-35)) = 70% of a quarter cycle or 17.5% of the cycle time. The late DQS shown by t3 is the reverse
situation and will have the DQS 17.5% of the cycle time after the clock.
Mn_CLK
ADRCTLearly
ADRCTLlate
DATAearly
DATAlate
DQSOUTearly
DQSOUTlate
DQS out delay from clock is -17.5% to +17.5% of cycle, set by difference between addr_skew and dqo_skew
Page 130 Section 6: DRAM
21) is about 16% of the cycle time when dqo_skew is 4'b0000, the maximum (shown as t7)
t0
Address delay from clock is 16%-34% of cycle set by addr_skew
t1
t5
Data delay from clock is 16%-34% of cycle set by addr_skew
t4
t2
t3

Figure 21: Timing Relationships Set by DLLs

B r oadco m C orp or ati on
DQS delay from data is 16%-34% of cycle set by dqo_skew
t7
t6
User Manual
10/21/02
Document 1250_1125-UM100CB-R