Table 311: Internal Register Addresses By Function - Broadcom BCM1250 User Manual

User Manual
10/21/02
I R
NTERNAL EGISTER
This section lists the registers and address assignments, per ZBbus agent. In the electronic version of the
document the Table/Page column provides a hyperlink to the table that defines the register.
Note: The following table details the specific addresses and names of each register. Each register is 1 byte, 2
bytes, 4 bytes or 8 bytes. Registers can be read or written as double-word (8 bytes), word (4 bytes), 2 byte or
signal byte access. Reads that are wider than the defined width or the register will return UNPREDICTABLE
data in the bits that are not defined. The address used to access the register will need to be adjusted if the
system is running in Big Endian mode. See
registers should be mapped in uncacheable space, so transactions will never be wider than 8 bytes (and will
never span more than an single 8 byte aligned range).
Reading registers marked 'Write Only' will give UNPREDICTABLE results. Writes to 'Read Only' registers will
be ignored.
Name
mc_config_0
mc_dramcmd_0
mc_drammode_0
mc_timing1_0
mc_timing2_0
mc_cs_start_0
mc_cs_end_0
mc_interleave_0
mc_cs0_row_0
mc_cs0_col_0
mc_cs0_ba_0
mc_cs1_row_0
mc_cs1_col_0
mc_cs1_ba_0
mc_cs2_row_0
mc_cs2_col_0
mc_cs2_ba_0
mc_cs3_row_0
mc_cs3_col_0
mc_cs3_ba_0
Document 1250_1125-UM100CB-R
S e c t io n 1 6 : R e f e r e n c e
A
DDRESSES BY
Section: "Internal Registers" on page 11

Table 311: Internal Register Addresses by Function

Table/
Address
Page
Memory Controller
72/135
00_1005_1100
75/139
00_1005_1120
76/139
00_1005_1140
77/140
00_1005_1160
78/141
00_1005_1180
79/141
00_1005_11a0
80/141
00_1005_11c0
81/142
00_1005_11e0
82/142
00_1005_1200
83/142
00_1005_1220
84/143
00_1005_1240
82/142
00_1005_1260
83/142
00_1005_1280
84/143
00_1005_12a0
82/142
00_1005_12c0
83/142
00_1005_12e0
84/143
00_1005_1300
82/142
00_1005_1320
83/142
00_1005_1340
83/142
00_1005_1360
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
F
UNCTION
Description
Channel 0 attributes.
Channel 0 SDRAM command.
Channel 0 SDRAM mode.
Channel 0 SDRAM timing 1.
Channel 0 SDRAM timing 2.
Channel 0 CS[3:0] start address.
Channel 0 CS[3:0] end+1 address.
Channel 0 interleaved CS position.
Channel 0 CS0 row address bits.
Channel 0 CS0 column address bits.
Channel 0 CS0 bank select.
Channel 0 CS1 row address bits.
Channel 0 CS1 column address bits.
Channel 0 CS1 DRAM bank select.
Channel 0 CS2 row address bits.
Channel 0 CS2 column address bits.
Channel 0 CS2 DRAM bank select.
Channel 0 CS3 row address bits.
Channel 0 CS3 column address bits.
Channel 0 CS3 DRAM bank select.
for details. Configuration
Section 16: Reference Page 445