Broadcom BCM1250 User Manual page 511

User Manual
10/21/02
Example Startup Code to clear the L2 Cache
Explicit Descriptor Interrupts
Feature Control 219
FIFO Configuration 351
Fixed Cycle Write Access 368
Flow Control 284
Flow control 294
flow control 152, 271
watermark 157
General Timers 58
general_timer_cfg 60
general_timer_cnt 60
general_timer_init_cnt 60
Generic Bus
address range 363
address space 362
burst mode 371
chip selects 362
data width 362, 365
error conditions 374
parity 364
Timing 365
Generic Bus Errors 374
Generic Bus Registers 375
GMII 264, 267
GPIO 397
GPIO Registers 399
gpio_clr_edge 54, 55, 398, 399
gpio_direction 397, 400
gpio_glitch 400
gpio_input_invert 397, 398, 399
gpio_int_type 54, 55, 398, 399
gpio_pin_clr 397, 400
gpio_pin_set 397, 400
gpio_read 397, 399
HDLC 180, 337, 344, 345,
Hint Based policy 122
Host Mode 190
HT 190
HyperTransport 190
Access to PCI 211
Additional Status Register 255
Bounce space 213
Bridge Command Register 247
Bridge Control Register 196, 249,
Bridge Primary (ZBbus) Status Register 248
Bridge Secondary (HT) Status Register 248
bus number 234
Command Register 249
COMPAT 195
Compatibility space 197
Configuration 194
configuration 234
configuration address 234
device number 234
Diagnostic Receive CRC Expected 255
Diagnostic Receive CRC Received 255
double-hosted chain 212
Document 1250_1125-UM100CB-R
99
158
F
G
H
347
260
B roa dcom Co rpo rat ion
BCM1250/BCM1125/BCM1125H
EOI 198
Error Control Register 253
Error Status Register 254
expansion space 194
function 234
generating interrupt messages
I/O space 195
interrupt acknowledgement
Isochronous BAR 252
isochronous bit 211
Isochronous Ignore Mask 253
Link Configuration Register 251
Link Control Register 250
Link Frequency Register 251, 252, 253
Little endian system 201
match bit lanes 203
match byte lanes 202
memory mapped 194
odering rules 231
Peer to peer 211
Read restrictions 200
register 234
SRI Command Register 252
SRI Data Buffer Allocation Register 254
SRI Transmit Buffer Count Max Register 255
SRI Transmit Control Register 254
subtractive decode 195
Target Done 236
When not used 236
HyperTransport Configuration Header
HyperTransport Expansion Space
HyperTransport Fabric to PCI Bus
HyperTransport Resets 260
I/O Bridge 1 157
I/O Bridge Clocks 32
IFG 269
Interface Overview 265
Interface to PHY 271
interrupt_diag 50, 52
interrupt_ldt 48, 49, 50, 52
interrupt_ldt_clr 52
interrupt_ldt_set 48, 52
interrupt_map 52
interrupt_mask 50, 52
interrupt_source_status 50, 52
interrupt_status 52
interrupt_trace 51, 52
interrupts
Arbitrated 49
Fixed 49
Non-vectored 49
IO_CLK100 31, 43
io_drive 379
io_ext_cfg 364, 365, 372, 375
io_ext_mult_size 363, 375
io_ext_start_addr 363, 376
io_ext_time_cfg_1 365
io_ext_time_cfg0 365, 373, 376
io_ext_time_cfg1 377
io_int_status 53
io_interrupt_addr 379
199
199
245
194
221
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