Table 183: Mac Status 1 Register; Table 184: Mac Debug Status Registers - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
Bits Name
52 tx_pause_on
63:53 reserved
Bits Name
63:0 status
Bits Name
63:0 status
Page 312 Section 9: Ethernet MACs
Table 182: MAC Status Registers
mac_status_0 - 00_1006_4408
mac_status_1 - 00_1006_5408
mac_status_2 - 00_1006_6408
READ ONLY - Reading this register will clear all latched bits
This register is used in both Ethernet and Packet FIFO modes
Default
1'b0 System revision PERIPH_REV3 or greater. This bit is set when the MAC has
received a pause frame and the pause time indicated has not expired. It is
cleared when the pause time expires (or if a pause freme with zero time is
received). No interrupt can be generated from this bit. Pause frames are not
used in Packet FIFO modes.
11'b0 Reserved

Table 183: MAC Status 1 Register

mac_status1_0 - 00_1006_4430
mac_status1_1 - 00_1006_5430
mac_status1_2 - 00_1006_6430
Reading this register will clear the channel 1 latched bits
This register is used in both Ethernet and Packet FIFO modes
Default
64'h0 Reading this register gives the same result as reading the status register, except
that only the latched bits associated with channel 1 transmit and receive DMA are
cleared. It is for use in split interrupt mode.

Table 184: MAC Debug Status Registers

mac_debug_status_0 - 00_1006_4448
mac_debug_status_1 - 00_1006_5448
mac_debug_status_2 - 00_1006_6448
This register is used in both Ethernet and Packet FIFO modes
Default
64'b0 Reading this register gives the same result as reading the status register, except
the bits are not cleared and none of the other side effects happen. It is intended for
debug accesses to the status.
B r oadco m C orp or ati on
(Cont.)
Description
READ ONLY
Description
READ ONLY
Description
User Manual
10/21/02
Document 1250_1125-UM100CB-R