Broadcom BCM1250 User Manual page 442

BCM1250/BCM1125/BCM1125H
In this example the chip select 0 timing registers are configured in one instruction bundle. The sync
instructions serve to pad out the bundle and prevent the next four instructions being fetched until the stores
have been issued (the SB-1 will only issue an uncacheable instruction fetch when the previous instructions
have graduated). The second group of four instructions write to the configuration to complete the setup and to
the system_cfg register to disable SMBus booting. Again the sync instructions are used to ensure these
writes have issued. This is sufficient to ensure the mode has changed and the next instruction fetch will be
serviced from the generic bus.
The second example is switching to the chip select 1 region at the same address. This can be done to move
to a generic bus device while leaving the SMBus mode enabled to allow a soft reset to revert back to SMBus
mode. Again care must be taken during the switch-over.
// Fetching from cs0 region from SMBus
// t0 points to generic CS0 config registers
// t1 points to generic CS1 config registers
// t2-7 have configuration values
addr:
addr+16:
addr+32:
// Fetched from cs1 on the generic bus
Here the timing is set for the chip select 1 region in the first instruction bundle. The second group sets the size
of the chip select 1 region, changes the base of chip select 0 to move it out of the way and configures the base
of chip select 1 to 00_1FC0_0000. It is important that the second group of instructions are together since they
change the target of the next instruction fetch. Again the sync instruction is used to ensure that the stores have
completed before the CPU will issue the next instruction fetch.
If the chip select region 1 were located at a different address then there would be no need to move the chip
select region 0 base address. In this case the two CS1 stores (of t5 and t7) would be the first two instructions
in the bundle, the third instruction would be the branch to the new address range and the sync would be in the
branch delay slot. Having the branch third and the sync in the delay slot will ensure that the stores are
completed (due to the sync and the SB-1 not fetching more instructions until the current ones graduate) and
the next instruction fetch comes from the chip select 1 space (because of the jump and the fact that its delay
slot is satisfied from the current instruction bundle).
Page 414 Section 14: Serial Configuration Interface
// this is on a cache block boundary
sh t2, io_ext_time_cfg0(t1)//set CS1 timing registers
sh t3, io_ext_time_cfg1(t1)
sh t4, io_ext_cfg(t1)//set CS1 config
sync
sh t5, io_ext_size(t1)//set CS1 size (to 0x3f = 4MB)
sh t6, io_ext_base(t0)//move CS0 base (to 00_2000_000)
sh t7, io_ext_base(t1)//set CS1 base (to 00_1FC0_0000)
sync
B r oadco m C orp or ati on
User Manual
10/21/02
Document 1250_1125-UM100CB-R