Table 280: Gpio Glitch Filter Select Register; Table 281: Gpio Direction Register; Table 282: Gpio Pin Clear Register; Table 283: Gpio Pin Set Register - Broadcom BCM1250 User Manual

User Manual
10/21/02
Bits Name
1:0 gpio_glitch
5:2 gpio_glitch
15:6 gpio_glitch
63:16 notimp
Bits Name
1:0 gpio_ddr
5:2 gpio_ddr
15:6 gpio_ddr
63:16 notimp
Bits Name
15:0 pin_clr
63:16 notimp
Bits Name
15:0 pin_set
63:16 notimp
Document 1250_1125-UM100CB-R

Table 280: GPIO Glitch Filter Select Register

gpio_glitch - 00_1006_1A98
Default
2'h0 When high the input from the pin has a 1ms glitch filter, when low a 60 ns glitch filter.
4'h0 When high the input from the pin has a 1ms glitch filter, when low a 60 ns glitch filter.
If generic bus parity is enabled these bits are ignored.
10'h0 When high the input from the pin has a 1ms glitch filter, when low a 60 ns glitch filter.
In PCMCIA mode these bits are ignored.
48'bx Not implemented.

Table 281: GPIO Direction Register

gpio_direction - 00_1006_1AA8
Default
2'h0 High for output driven from the output latch, low for input. If the synchronous serial
interface RstrobeOut output is enabled this register is ignored and the pin will be an
output.
4'h0 High for output, low for input. When generic bus parity is enabled these bits are
ignored.
10'h0 High for output, low for input. When PCMCIA is enabled these bits are ignored.
48'bx Not implemented.

Table 282: GPIO Pin Clear Register

gpio_pin_clr - 00_1006_1AB0
Default
16'h0 Writing a 1 to a bit position will clear that bit in the output latch.
48'bx Not implemented.

Table 283: GPIO Pin Set Register

gpio_pin_set - 00_1006_1AB8
Default
16'h0 Writing a 1 to a bit position will set that bit in the output latch
48'bx Not Implemented.
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Description
Description
WRITE ONLY
Description
WRITE ONLY
Description
Section 13: GPIO Page 399