Table 77: Sdram Timing Register - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
Bits Name Default
34:32 dram_type 3'b0
35 large_mem 1'b0
36 pre_on_A8 1'b0
37 ram_with_A13 1'b0
63:38 reserved 26'b0
Bits Name Range
3:0 tRCD 1-6
6:4 tCrD 1-6
7 tCrDh 0-1
11:8 tCwD 1-2 or
1-4
15:12 reserved 0
19:16 tRP 1-4
23:20 tRRD 1-4
27:24 tRCw-1 1-15
31:28 tRCr-1 1-15
35:32 reserved 0
39:36 reserved 0
43:40 tCwCr 0-15
47:44 reserved 0
51:48 reserved 0
55:52 tRFC 0-15
59:56 tFIFO 0-1
Page 140 Section 6: DRAM
Table 76: DRAM Mode Register
mc_drammode_0 - 00_1005_1140
mc_drammode_1 - 00_1005_2140
DRAM type:
000: JEDEC DDR (one DQS for every 8 DQ bits)
001: FCRAM
010: DDR SGRAM (one DQS for every 32 DQ bits)
Others Reserved
If this bit is set large memory support (using an external chip select decoder) is enabled.
See Section: "Larger Memory Systems" on page
If this bit is set the AutoPrecharge flag will be output on the A8 address bit rather than
A10. (Only supported on parts with system revision PERIPH_REV3 or greater).
This bit should be set when the large_mem bit is set if the row address uses A13. It
causes the CS[3:2] to be driven from bits [15:14] of the row address mask. It also needs
to be set to cause BA[2] to be output on A13 rather than A12 for non-standard 8 bank
DRAMs. (Only supported on parts with system revision PERIPH_REV3 or greater).
Reserved

Table 77: SDRAM Timing Register

mc_timing1_0 - 00_1005_1160
mc_timing1_1 - 00_1005_2160
Default
4'h3 RAS to CAS delay. This should be set to 1 for FCRAMs.
3'h2 Cycles from CAS(read) to data (the CAS latency).
1'b0 If this bit is set the data capture is delayed by a half cycle from the integer part
of the CAS latency set in tCrD. See the discussion in
Guidelines" on page
4'h1 Delay from CAS to Write data.
On parts with system revision PERIPH_REV3 or greater the range is extended
to 1-4.
4'h0 Reserved
4'h4 Cycles required from PRECHARGE to RAS.
4'h2 Cycles required from RAS to RAS for a different bank.
4'ha One less than cycles required from RAS(write) to next RAS of the same bank.
4'h9 One less than cycles required from RAS(read) to next RAS of the same bank.
4'h0 Reserved
4'h0 Reserved
4'h4 Cycles of separation from write to read.
This field is calculated as: tCwCr = tRCw - (tRCD + tCwD + 2 + tWTR)
Note that tRCw is one greater than the value set in tRCw-1 field and tWTR is
the internal write to read delay for the SDRAM (normally specified as 1 cycle).
4'h0 Reserved
4'h0 Reserved
4'hc Cycles required from Auto-refresh to Active or Auto-refresh.
4'h1 Additional cycles required for data capture FIFO.
B r oadco m C orp or ati on
(Cont.)
Description
124.
Description
131.
Document
User Manual
10/21/02
"Timing Parameter
1250_1125-UM100CB-R