Broadcom BCM1250 User Manual page 57

User Manual
10/21/02
IO_AD
Name
Bit
24 ldt_test_en
25 gen_parity_en
31:26 config
After a system reset (or power-on reset) CPU 0 and all peripherals are brought out of reset, but on a BCM1250
CPU 1 continues to be held in reset and will be isolated from the system. This allows CPU 0 to perform
essential system initialization before releasing CPU 1. Since both CPUs have the same reset vector (virtual
FFFF_FFFF_BFC0_0000, physical 00_1FC0_0000) the initial code will probably branch based on the CPU
number which can be read from the PrId CP0 register.
The boot address is in the space that the I/O system uses for the generic expansion bus. At reset time this is
configured to allow access to a (slow) boot ROM or flash memory, or can be diverted to SMBus interface 0,
which will fetch code from a serial EEPROM. (A debugger may use the EJTAGBOOT option to cause the CPU
to fetch the boot code from the JTAG port as described in
Following reset, no coherent accesses should be made until the data cache tags in the CPU(s) and the L2
cache tags have been invalidated. The DMA controllers and requests from the expansion buses can use
coherent accesses, so they must not be used until the tags have been cleared. On a single CPU, once the
level 1 cache tags have been invalidated cacheable non-coherent accesses may be done to the boot memory
space. It is recommended that CPU 0 invalidates its cache tags and the L2 cache tags prior to releasing CPU 1
from reset, CPU 1 should clear its tags and signal CPU 0 that coherent accesses may be used.
It is possible to independently reset the CPUs, either from software or the watchdog timers. This is a potentially
hazardous operation since while in reset the CPU is removed from participation in the coherence protocol.
When the CPU goes in to reset it may be in the process of supplying data and releasing a exclusive lock on a
line, since these operations are aborted some other agent may hang waiting for the data or lock. When the
CPU is released from reset it will have stale coherency information in its caches and software initialization will
clear all state. The independent reset features can be used to implement error recovery when one CPU fails
while maintaining availability by allowing the other to continue to operate, but very careful consideration must
be given to the possible state of the system if this is done (or it may be optimistically done with the fall-back
position of a full reset if the partial restart fails).
Document 1250_1125-UM100CB-R
Table 8: Static Configuration Options
Pulled Up to 3.3V
Broadcom Use Only.
Enable HyperTransport test
mode.
Parity is enabled on the generic
bus. GPIO[5:2] are used by the
Generic Bus controller.
Sampled at reset time and available in the SCD configuration
register. These bits can be interpreted by software for system
configuration.
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
(Cont.)
Pulled Down
Normal Operation.
Parity is not used on the
generic bus GPIO[5:2] are
GPIO pins.
Section: "EJTAGBOOT Instruction" on page
Section 3: System Overview
Section
N/A
Section: "Generic
Bus
Parity" on page 364.
N/A
426.)
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