Broadcom BCM7405 Video Set-Top Box Manuals

Manuals and User Guides for Broadcom BCM7405 Video Set-Top Box. We have 1 Broadcom BCM7405 Video Set-Top Box manual available for free PDF download: General Information Manual

Broadcom BCM7405 General Information Manual

Broadcom BCM7405 General Information Manual (194 pages)

PRELIMINARY HARDWARE DATA MODULE

Brand: Broadcom | Category: Control Unit | Size: 3 MB

Table of Contents

Table of Contents
3
Document Overview

15
- Overview
  15
- Table 1-1: Document Overview
  16
Functional Description

17
- Top-Level Overview
  18
  - Unctional Escription
    18
  - Features
    19
  - Figure 1-1: Functional Block Diagram
    21
- Video Data Flow
  22
  - Overview
    22
  - Compressed Video Input
    22
  - Figure 1-2: Video Data Flow Diagram
    22
  - Personal Video Recording
    23
  - Digital Video Decompression
    23
  - ITU-R 656 Input
    23
  - Video Processing
    23
  - Video Encoder
    24
  - Video Dacs
    24
  - Table 1-2: Video DAC Configuration
    24
- Data Transport Processor
  25
  - Overview
    25
  - Features
    25
  - Functional Overview
    27
  - Figure 1-3: Data Transport and Broadcom Security Processor Block Diagram
    28
  - Table 1-3: Definition of Terms
    29
  - Data Transport I/O Connections
    30
    
    Data Transport Input Bands
    30
    
    Figure 1-4: Data Transport I/O Connections Diagram
    30
    
    Throughput Data Rate
    30
    
    Packet Input Buffer
    31
    
    PID Parser
    31
    
    Pid/Packet Substitution and Generation Module
    32
    
    Multistream Cablecard Interface
    33
    
    Condition Access Descramblers (the Downstream Descramblers)
    34
    
    Copy Protection
    34
    
    NDS ICAM Module
    34
    
    PES Parser
    35
    
    PSI Section Filter and Processor
    35
    
    Interrupt Controller
    36
    
    Memory Buffer Manager
    36
    
    Record Audio Video Engine (RAVE)
    36
  - Audio/Video Interface
    39
  - Playback
    39
  - Playback Sync Extractor
    40
  - Remux Module
    40
  - PCR Recovery Block
    41
  - Serial STC Broadcast Module
    42
- Broadcom Security Processor
  42
- Advanced Video Decoder
  43
  - MPEG-4 Part2
    44
  - DIVX
    44
  - VC-1
    44
  - XVID
    45
  - Features
    45
  - Supported Picture Sizes
    45
  - Output Data Format
    45
  - AVD Block Diagram and Data Flow Description
    46
  - Figure 1-5: Advanced Video Decoding Module Block Diagram
    46
- Advanced Audio Module
  47
  - Figure 1-6: Audio Block Diagram
    47
  - Features
    48
  - Overview of Audio Module
    49
- Video and Graphics Display
  50
  - Overview
    50
    
    Features
    50
    
    Video Subsystem
    50
    
    Table 1-4: Decode and Display Formats
    51
    
    Graphics Subsystem
    52
  - Top Level Partitioning
    52
    
    Figure 1-7: Video and Graphics Block Diagram
    52
    
    Figure 1-8: Video Display Engine Block Diagram
    53
    
    AVC/MPEG-2/VC-1 Feeder
    54
    
    Graphics Feeder
    54
    
    Video Feeder
    54
    
    Motion Adaptive De-Interlacer
    55
    
    Video Scaler
    55
    
    Capture Block
    56
    
    Compositor
    56
    
    Film Grain Technology
    56
    
    Digital Contour Removal
    57
    
    Digital Noise Reduction
    57
    
    DNR Operations
    57
    
    Graphics Subblock Description
    58
    
    Figure 1-10: Memory-To-Memory Compositor Block Diagram
    59
    
    Scaler Overview
    59
    
    Feeder Architecture (Source and Destination)
    60
    
    Figure 1-11: Stripe Example
    60
    
    Color Keying and Color Matrix Architecture
    61
    
    Compositor Architecture
    62
    
    Figure 1-12: Color Keying Flow
    62
    
    Table 1-5: Color and Alpha Selection
    62
    
    Capture Architecture
    63
    
    ROP Architecture
    63
    
    Analog Video Encoder
    64
    
    Digital Video Decoder (ITU-R-656)
    64
    
    Table 1-6: Digital Video Decoder Supported Modes
    64
    
    Table 1-7: VBI Decoding
    64
    
    VBI Decoding
    64
    
    Table 1-8: Analog Video Encoder
    65
    
    Figure 1-13: VEC Block Diagram
    66
    
    Table 1-9: VBI Encoding
    66
    
    VBI Encoding
    66
    
    Digital Video Encoder
    67
    
    Safe Mode
    67
    
    Video Dacs
    67
    
    Supported Modes
    68
    
    Table 1-10: DVI Supported Modes
    68
    
    Table 1-11: ITU-656 Supported Modes
    68
    
    Supported PC Scan Rates
    69
    
    Table 1-12: DVI PC Scan Clock Rates
    69
    
    Table 1-13: PC Display Support
    69
  - RF Modulator
    70
    
    Features
    70
    
    Figure 1-14: RF Modulator Block Diagram
    70
    
    Overview
    70
    
    Supported Television Standards
    71
    
    Table 1-14: Supported Modulation Standards
    71
    
    Typical Usage Modes
    71
    
    Audio Transmission Modes
    72
    
    Baseband BTSC Composite Output Mode
    72
    
    Sound if Output Mode
    72
    
    Table 1-15: RFM Audio Usage Modes for Normal Operation
    72
    
    Unsupported Audio Mode
    72
  - Memory Controller
    73
    
    Overview
    73
    
    Figure 1-15: Memory Controller Partition
    74
    
    DRAM Physical Layer Controller
    75
    
    Memory Configurations Supported
    75
    
    Arbitration
    76
    
    Buses
    76
    
    DDR-SDRAM Memory Image Organization
    76
    
    Digital Video Compression Standards
    76
    
    DRAM Transaction Layer Controller
    76
    
    Memory Accesses for Video Decompression
    76
  - DDR Clock Generation
    76
- MIPS4380 Processor Core
  77
  - Overview
    77
  - Architecture
    77
  - Micro-Architecture
    78
  - EJTAG Debug Support
    78
  - Major Functional Blocks
    79
    
    Execution Unit
    79
    
    Figure 1-16: Block Diagram of the CPU
    79
    
    Floating-Point Unit
    80
    
    Multiply Divide Unit
    80
  - Edsp Extended Instructions
    81
  - Memory Management Unit with TLB
    81
  - Table 1-16: FPU Latency and Repeat Rate
    81
  - System Control Coprocessor (CP0)
    82
  - Instruction Cache
    82
  - Data Cache
    82
  - Level-Two Cache
    83
  - Readahead Cache
    83
  - Little and Big Endianness of Byte Ordering
    83
  - Figure 1-17: Little and Big Endian Byte Ordering
    83
  - Debugging Support Unit
    84
- Peripherals
  85
  - Overview
    85
  - Peripheral Control Unit
    85
  - Keypad Controller
    85
  - LED Controller
    85
  - IR Receiver Controller
    85
  - IR Blaster Controller
    86
  - Figure 1-18: Flash IR Scheme Example
    86
  - Figure 1-19: IR Blaster Block Diagram
    86
  - UHF Receiver
    88
  - Figure 1-20: Analog Front End of UHF Receiver with External Components
    88
  - Uart
    89
    
    Figure 1-21: Digital Front End of UHF Receiver
    89
    
    General Description
    89
    
    Figure 1-22: UART Functional Block Diagram
    90
    
    Figure 1-23: Asynchronous Serial Data Waveform (01001011 Data, 8-Bit Character, Even Parity)
    90
    
    Functional Description
    90
    
    Generic I/O Port Controller
    91
    
    SPI Master
    91
    
    BSC Master
    92
    
    Programmable Queue
    92
    
    Programmable Queue Pointer
    92
    
    Programmable Transfer Delay
    92
    
    Programmable Transfer Length
    92
    
    Wraparound Transfer Mode
    92
    
    BSC Master Interface Operation
    93
    
    BSC Operation
    93
    
    BSC Slave
    93
    
    Figure 1-24: Variable-Frequency PWM Generation Diagram
    94
    
    Pwms
    94
    
    Smart Card Interfaces
    94
    
    Timer/Counters
    94
    
    Features
    95
    
    Figure 1-25: Smart Card Interface Block Diagram
    95
    
    Figure 1-26: M-Card CPU Interface
    96
    
    Introduction
    96
    
    M-Card CPU Interface
    96
    
    Figure 1-27: MCIF Interfaces
    97
    
    Input and Output Processes
    97
    
    PCI and External Bus Interface
    98
    
    Figure 1-28: EBI Synchronous Read Cycle between Two PCI Cycles
    99
    
    Figure 1-29: EBI Asynchronous Read Cycle between Two PCI Cycles
    100
    
    Figure 1-30: EBI Asynchronous Write Cycle between Two PCI Cycles
    101
    
    Figure 1-31: EBI Synchronous Write Cycle between Two PCI Cycles
    102
    
    Advanced Connectivity Interface
    103
    
    Ethernet
    103
    
    Serial ATA Controller
    103
    
    Figure 1-32: SATA Core Block Diagram
    104
    
    Usb
    104
    
    Figure 1-33: Soft Modem Connections
    105
    
    JTAG Interface
    105
    
    Pci
    105
    
    Soft Modem
    105
  - Testability
    106
    
    Built-In Self-Test
    106
    
    Functional Testing
    106
    
    On-Board Testing
    106
    
    Overview
    106
    
    Production Testing
    106
    
    Scan
    106
    
    Test Buses
    106
    
    Test Modes
    106
    
    Power Features
    107
    
    Table 1-17: Power Estimate
    107
    
    Table 1-18: Power Configuration Example
    107
    
    Figure 1-34: Power-Up Sequence Waveforms Without On-Chip Voltage Regulator
    108
Hardware Signal Descriptions

109
- Pin Definition Notations
  110
- Table 1-19: Pin Descriptions
  110
- Table 1-20: Power-On Strap Settings
  161
Timing and AC Characteristics

163
Crystal Requirements

183
Electrical Characteristics

185
- Table 1-41: Absolute Maximum Ratings
  186
- Table 1-42: Recommended Operating Conditions
  186
Thermal Data

187
- Table 1-43: Thermal Data (Without External Heat Sink, 2S2P Board)
  188
Mechanical Characteristics

189
Ordering Information

193
- Table 1-44: Ordering Information
  194

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