Figure 87: Jtag Hypertransport Input Boundary Scan Block - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
The HyperTransport input block, shown in
However, these will always be inverses when a correct differential signal is received. The outputs of the BC_1
cells can be used to drive the single data rate version of the data into the part simplifying INTEST vector
injection.
in_posedge
in_negedge
The order of the input/output pins are shown in the BSDL file for the part.
BSRMODE - H
Using the normal JTAG definition it is not possible to keep the boundary scan register active (driving pins or
into the part) and scan other internal registers, because the boundary scan must be made inactive when a non-
BSR instruction is scanned in to the instruction register. The large ammount of internal state in the part makes
it useful to be able to do this so the BSRMODE instruction has been added. If the BSRMODE instruction is
used after EXTEST, CLAMP or INTEST then the BSR mode is maintained (keeping the signals driven from
the BSR) even if another JTAG instruction is used. This allows any number of other chains to be scanned while
the BSR values are held. If EXTEST, CLAMP or INTEST is followed by any instruction other than BSRMODE
the BSR mode is removed (per the standard JTAG behaviour). After BSRMODE has been used its state should
be cleared by performing one of the BSR instructions followed by a non-BSR instruction.
Page 434 Section 15: JTAG and Debug
Mode
intest
TDO
update_dr

Figure 87: JTAG HyperTransport Input Boundary Scan Block

B
OLDING OUNDARY
B r oadco m C orp or ati on
Figure 87, is similar. It uses two BC_1 cells to monitor the two pins.
ldt_rx_clk
TDI
shift_dr
clock_dr
S A
CAN CTIVE
User Manual
10/21/02
RX_p
RX_n
Document 1250_1125-UM100CB-R