Broadcom BCM1250 User Manual page 9

User Manual
10/21/02
Big Endian System: Match Byte Lanes ............................................................................................... 202
Big Endian System: Match Bit Lanes .................................................................................................. 203
Viewing Endian Policy as an Optimization .......................................................................................... 204
Accessing the SiByte from PCI Devices ................................................................................................ 205
Accessing the SiByte from HyperTransport Devices ........................................................................... 210
Force Isochronous Mode Address Range ................................................................................... 212
Accessing the SiByte from a SiByte on a Double Hosted Chain......................................................... 212
HyperTransport Bounce Space........................................................................................................... 213
Performance of the PCI and HyperTransport Interfaces ...................................................................... 213
Accesses from the SiByte to the PCI or HyperTransport .................................................................... 214
Accesses from the HyperTransport to the SiByte ............................................................................... 216
Accesses from the PCI to the SiByte .................................................................................................. 217
PCI Adaptive Retry ...................................................................................................................... 217
Peer-to-Peer Accesses ............................................................................................................................ 219
PCI Bus To HyperTransport Fabric..................................................................................................... 219
HyperTransport Fabric to PCI Bus ...................................................................................................... 221
PCI Arbiter ................................................................................................................................................ 222
PCI Interrupts ........................................................................................................................................... 222
HyperTransport Differences from Revision 0.17 Specification ........................................................... 222
HyperTransport Differences from Revision 1.03 Specification............................................................ 224
Ordering Rules.................................................................................................................................... 231
Using the PCI in Device Mode................................................................................................................. 232
Configuration of PCI and HyperTransport ............................................................................................. 234
HyperTransport Target Done Counter ................................................................................................ 236
Systems That Do Not Use HyperTransport......................................................................................... 236
Configuration Header Descriptions ..................................................................................................... 236
PCI Configuration Header ................................................................................................................... 236
HyperTransport Configuration Header ................................................................................................ 245
System Reset Initialization of the HyperTransport Interface ............................................................... 256
Configuration Flags in the SriCmd Register................................................................................. 257
Timing Registers: SriRxDen, SriTxDen, SriRxNum and SriTxNum ............................................. 257
Receive Pointer Margin Control in SriCmd Register.................................................................... 258
Transmit Pointer Initial Offset in the SriCmd Register ................................................................. 259
Error Control Register .................................................................................................................. 259
Transmit Control Register ............................................................................................................ 259
Document 1250_1125-UM100CB-R
B roa dcom Co rpo rat ion
BCM1250/BCM1125/BCM1125H
Page ix