Section 3: System Overview; Introduction; Figure 5: Logical Block Diagram Of Bcm1250 And Bcm1125/H - Broadcom BCM1250 User Manual

User Manual
10/21/02
I
NTRODUCTION
A logical block diagram of the BCM1250 and BCM1125/H family is shown in
exactly match the implementation details, but it gives a more useful model for programmers and system
designers to use. The system is based around the ZBbus, a high speed split-transaction multiprocessor bus.
It connects the CPU(s), the level 2 cache (L2), the memory controller, two I/O bridges and the System Control
and Debug unit (SCD).
System Control & Debug
JTAG
Performance
Monitor
Interrupt
Mappers
Timers
Generic
Data Mover
PCI
Host
Bridge
as if bridge from PCI
PCI
Bus
BCM1125 Only PCI
BCM1250, BCM1125H PCI & HT
Document 1250_1125-UM100CB-R
Sec t ion 3 : Sys t em Over view
Trace
Buffer
Bus Trace
Controller
Data
Bus Error
Log/Counters L1
Address Trap
I/O
Bridge 0
HT
DMA
Host
MAC0
Bridge
HT configured
HT
G/MII
Fabric

Figure 5: Logical Block Diagram of BCM1250 and BCM1125/H

B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Only in BCM1250
SB-1 SB-1
CPU 0 CPU 1
Inst. Data Inst.
L1 L1 L1
ZBbus
I/O
Bridge 1
DMA DMA DMA DUART
MAC1 MAC2 Serial0 A
G/MII G/MII Serial0
Only in
BCM1250
Figure 5. This figure does not
DDR SDRAM
Ch1 Ch0 Only in
BCM1250
Memory
Controller
L2
Address/Response
Data
DMA SMBus Generic
Bus
B Serial1 Master
Bridge
Serial1 SMB0 SMB1 Generic
Bus

Section 3: System Overview

PCMCIA
Control
& GPIO
PCMCIA
&
GPIO
Page 9