Broadcom BCM1250 User Manual page 16

BCM1250/BCM1125/BCM1125H User Manual
10/21/02
Figure 33: Example 1 - TCP checksum a packet............................................................................................181
Figure 34: Example 2 - Preparing an iSCSI packet ........................................................................................182
Figure 35: Example 3 - Fragmenting an iSCSI packet....................................................................................183
Figure 36: PCI and HyperTransport Organization ..........................................................................................191
Figure 37: Address Ranges for CPU Access to PCI and HyperTransport ......................................................193
Figure 38: Little Endian System ......................................................................................................................201
Figure 39: Match Byte Lane Endian Policy .....................................................................................................202
Figure 40: Match Bit Lane Endian Policy ........................................................................................................203
Figure 41: PCI BAR0 Address Mapping Table ...............................................................................................206
Figure 42: Default Host Mode Memory Map from PCI Bus Master.................................................................209
Figure 43: Memory Map From HyperTransport Device...................................................................................210
Figure 44: Buffers Used for Accesses from the ZBbus to PCI and HyperTransport .......................................214
Figure 45: Buffers Used for DMA Accesses from the PCI and HyperTransport .............................................216
Figure 46: PCI Adaptive Retry Parameters.....................................................................................................218
Figure 47: Buffers Used for PCI to HyperTransport Peer-to-Peer Accesses ..................................................220
Figure 48: Buffers Used for HyperTransport to PCI Peer-to-Peer Accesses ..................................................221
Figure 49: Configuration Space Address ........................................................................................................234
Figure 50: HyperTransport Interface Clocks and FIFOs .................................................................................256
Figure 51: Ethernet Interface Block Diagram ..................................................................................................265
Figure 52: Ethernet Frame Format .................................................................................................................268
Figure 53: Prepended Header Format ............................................................................................................270
Figure 54: Transmit FIFO Thresholds .............................................................................................................272
Figure 55: Receive FIFO Thresholds ..............................................................................................................275
Figure 56: Receive Address Filter...................................................................................................................278
Figure 57: Receive Channel Selection............................................................................................................281
Figure 58: Selecting the Channel Offset .........................................................................................................281
Figure 59: MDIO Flows ...................................................................................................................................288
Figure 60: 8-bit Packet FIFO GMII Style .........................................................................................................295
Figure 61: 8-Bit Packet FIFO Encoded Style ..................................................................................................296
Figure 62: 8-Bit Packet FIFO SOP Style ........................................................................................................297
Figure 63: 8-Bit Packet FIFO EOP Style ........................................................................................................298
Figure 64: 16-Bit GMII Style Packet FIFO ......................................................................................................299
Figure 65: 16-Bit Encoded Packet FIFO ........................................................................................................300
Figure 66: UART Interrupt Generation ............................................................................................................325
Figure 67: Synchronous Interface Block Diagram ..........................................................................................338
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