Interrupts; Table 18: Interrupt Mappings - Broadcom BCM1250 User Manual

User Manual
10/21/02
I
NTERRUPTS
The chip has a large number of interrupt sources. These come from both internal peripherals and external
signals. Each CPU has its own interrupt mapper which allows the destination of the interrupt from each source
to be set to one of the six architected hardware interrupts, the non-maskable interrupt (NMI) or the Debug
Interrupt (DINT). The mapper block includes the CPU mailbox registers described in the previous section.
Most interrupt sources are common to each interrupt mapper. The only sources that are specific to a CPU are
directed interrupts from the HyperTransport (as described below, the interrupt message includes which CPU
it should be delivered to) and the per-CPU mailbox interrupts.
The basic operation of the interrupt mapper is described in this section. Interrupts from the HyperTransport
fabric extend the basic model as described in the next section.
has a diagram of the complete mapper, including system, mailbox and HyperTransport sources and describes
all the associated registers.
The interrupt mapper receives the level sensitive interrupts from all sections of the part. Each source has an
associated mask bit and a 3 bit map register. If the source is interrupting and not masked out it is driven to one
of the CPU interrupt lines according to the mapping.
bit in the Cause register.
Mapping Interrupt
000 I0
001 I1
010 I2
011 I3
100 I4
101 I5
110 NMI
111 DINT
Each source maps to one CPU interrupt line. There is no limit on how many sources may map to a single CPU
line. The I5 interrupt line is also used by interrupts generated internal to the CPU, these will be merged with
any external requests. The MIPS architecture uses software based interrupt dispatch, so the software can
assign priorities to the six regular interrupt lines as it sees fit. A typical system would merge most of the system
sources on a few of the interrupt lines, and assign one source per line for sources that need rapid dispatch.
Document 1250_1125-UM100CB-R

Table 18: Interrupt Mappings

CP0 Cause Register
IP[2] bit 10.
IP[3] bit 11.
IP[4] bit 12.
IP[5] bit 13.
IP[6] bit 14.
IP[7] bit 15.
Reset/NMI vector, flagged in status register not cause register.
CPU debug interrupt, flagged in debug register.
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Section: "The Full Interrupt Mapper" on page 50
Table 18 shows the mapping, and the corresponding IP
Section 4: System Control and Debug Unit Page 47