Table 46: Trace Event Register - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
Each trigger event has a counter associated with it. If the counter is greater than zero when the trigger condition
is true then the counter decrements. If the counter is zero then the event is signaled to the trigger sequencers,
and the counter will be reloaded with its initial value.
The trace event register is shown in
Bits Field
3:0 Addr_match[3:0]
4 req_id_match
5 data_id_match
6 resp_id_match
7 interrupt
8 reserved
9 debug_pin
10 write
11 read
15:12 req_id[3:0]
19:16 resp_id[3:0]
23:20 data_id[3:0]
31:24 count[7:0]
Page 72 Section 4: System Control and Debug Unit
Table 46. There are eight such registers trace_event_0 to trace_event_7.

Table 46: Trace Event Register

trace_event_0 - 00_1002_0A20
trace_event_1 - 00_1002_0A28
trace_event_2 - 00_1002_0A30
trace_event_3 - 00_1002_0A38
trace_event_4 - 00_1002_0A60
trace_event_5 - 00_1002_0A68
trace_event_6 - 00_1002_0A70
trace_event_7 - 00_1002_0A78
Default
4'b0 Each of these bits corresponds to an address trap register (see
Trapping" on page
is not considered as part of the trigger. If any of these bits are set then the address
is considered part of the trigger, and the event only triggers if the address falls
within the range specified by the corresponding trap. Both simple and complex
traps may be used. The event will trigger whenever there is a hit in the trap, the
occurrence counter in the trap is ignored.
1'b0 When set the address portion of the event only occurs if the requester ID of the
transaction matches the req_id field of this register.
1'b0 When set the data portion of the event only occurs if the data ID of the transaction
matches the data_id field of this register.
1'b0 When set the data portion of the event only occurs if the responder ID of the
transaction matches the resp_id of this register.
1'b0 When set the event occurs when an interrupt that is enabled for tracing occurs.
The int_trace_trigger outputs from the two interrupt mappers (see
Figure 10 on page
of which interrupt triggered the event). The event triggers once on the assertion
of the OR of the two interrupt mapper outputs. Before the event can trigger again
the outputs of both mappers must be deasserted.
1'b0 Reserved
1'b0 When set the event occurs if the external debug pin is pulled low. The event will
trigger once on the falling edge of the DEBUG_L pin. DEBUG_L must return to its
deasserted (high) state before the event will trigger again.
1'b0 When set the event only occurs if the transaction is a write.
1'b0 When set the event only occurs if the transaction is a read.
4'b0 Requester ID used for matching.
4'b0 Responder ID used for matching.
4'b0 Data ID used for matching.
8'b0 If the count is not 0 then the event does not take place. Instead the counter is
decremented. If the counter is 0 then the event occurs and the count is restored
to its initial value.
Writing this register sets the initial value of the counter, reading will return the
current value.
B r oadco m C orp or ati on
Description
67). If none of these bits are set then the address on the bus
51) are ORed together to signal the event. (No record is made
User Manual
10/21/02
Section: "Address
Document 1250_1125-UM100CB-R