Receiver Operation; Receiver Configuration; Figure 55: Receive Fifo Thresholds - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
R O
ECEIVER PERATION
R C
ECEIVER ONFIGURATION
The receive fifo is a 64 bit wide fifo with 64 entries. When the FIFO contains data it will signal the DMA engine
to request emptying. The rx_rd_thrsh field in the mac_thrsh_cfg register sets the number of valid entries that
must be in the FIFO to request emptying. The DMA engine transfers in blocks of 32 bytes so this field should
normally be set to four entries. The threshold is overridden when the end of a packet is in the FIFO, since these
are unlikely to be correctly aligned.
The receiver will hold off informing the DMA engine of the arrival of a new packet until successful reception of
the first few bytes. The rx_rl_thrsh field in the mac_thrsh_cfg register sets the number of entries that must be
written to the FIFO before it signals that data is available. If the end of the packet is received the data is always
reported to the DMA engine. If there is any reception error before this point then the packet can be
automatically dropped by flushing the data in the FIFO. The error will still be counted in the error statistics. If
the drp_errpkt_en bit in the mac_cfg register is set then all packets with errors will be thrown on the ground in
this way. If this bit is clear then more selective bits in the mac_cfg determine whether packets with errors are
dropped or delivered with an error status. Regardless of any of these settings, errors that are detected after
the rx_rl_thrsh threshold has passed are always delivered with an error status.
For example, if the rx_rl_thrsh is set to 8 and the MAC detects a runt packet (shorter than the 64 byte minimum
size Ethernet packet) the DMA engine will never be told about the packet and it will be automatically discarded.
Page 274 Section 9: Ethernet MACs
Start of
Packet
S
64 bit wide
O
P
rx_rl_thrsh
rx_rd_thrsh
Once the rl_thrsh has been passed
the FIFO signals data available if
this number of entries are valid
or this range contains the end of
packet

Figure 55: Receive FIFO Thresholds

B r oadco m C orp or ati on
Errors that happen between SOP
and here can cause the packet
to be dropped
Document 1250_1125-UM100CB-R
User Manual
10/21/02