Interrupts; Figure 66: Uart Interrupt Generation - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
I
NTERRUPTS
The DUART interrupts are provided as system interrupts 8 (for channel A) and 9 (for channel B). The conditions
that can cause an interrupt are signalled in the interrupt status register duart_isr. This contains the channel A
status in the lower four bits and the channel B status in the upper four bits. For convenience the information
for each channel is available in the duart_isr_a and duart_isr_b registers where the status for the channel is
always in the lower four bits and the upper bits are zeros. The conditions that can cause an interrupt are:
transmitter ready, receiver ready or receiver FIFO full, break detected or removed and change detected on the
handshake lines. Corresponding to each bit in the interrupt status register there is a bit in the interrupt mask
register duart_imr, if a status bit is set and the corresponding mask bit is also set then an interrupt will be
raised. Again, for programming convenience, aliases of the lower and upper bits of the mask are provided in
the lower four bits of the duart_imr_a and duart_imr_b registers (these are aliases - internally there is only a
single copy of each mask bit).
Figure 66 shows the interrupt generation for a single channel.
rx_break
reset_break_command
CtsTclkIn
CinRclkIn
Page 324 Section 10: Serial Interfaces
duart_mode[5] tx_irqsel
tx_FIFO_empty
tx_ready
duart_mode[6] rx_irqsel
rx_FIFO_not_empty
1
rx_FIFO_full
0
State Change
S
Detect
R
State Change
S
Detect
R
duart_ipcr[0] (ch A)
duart_ipcr[1] (ch B)
State Change
S
Detect
R
duart_ipcr[2] (ch A)
duart_ipcr[3] (ch B)
duart_ipcr_read

Figure 66: UART Interrupt Generation

B r oadco m C orp or ati on
1
0
duart_aux[0] (ch A)
duart_aux[1] (ch B)
duart_ipcr[4] (ch A)
duart_ipcr[5] (ch B)
duart_aux[2] (ch A)
duart_aux[3] (ch B)
duart_ipcr[6] (ch A)
duart_ipcr[7] (ch B)
User Manual
[0]
duart_imr[3:0] (ch A)
duart_imr[7:4] (ch B)
[1]
interrupt
[2]
[3]
Document 1250_1125-UM100CB-R
10/21/02