Broadcom BCM1250 User Manual page 7

User Manual
10/21/02
Cache Configuration Register ............................................................................................................... 99
Example Startup Code to clear the L2 Cache....................................................................................... 99
Registers ................................................................................................................................................... 100
Section 6: DRAM .............................................................................................................. 103
Introduction .............................................................................................................................................. 103
A Comment on the term Bank............................................................................................................. 103
Memory Controller Architecture ............................................................................................................. 104
Memory Access Sequencing .............................................................................................................. 107
Clock Ratios and Clocking Scheme ....................................................................................................... 107
Memory Configurations ........................................................................................................................... 109
Mapping .............................................................................................................................................. 109
Channel Select.................................................................................................................................... 109
Chip Select.......................................................................................................................................... 110
Example Channel and Chip Select Configurations ............................................................................. 112
Row, Column and Bank Configuration................................................................................................ 117
Choosing Interleave Parameters ........................................................................................................ 120
Page Policy ......................................................................................................................................... 122
Supported DRAMs and DIMMs........................................................................................................... 123
DDR SDRAMS............................................................................................................................. 123
DDR FCRAMs ............................................................................................................................. 123
DIMMs ......................................................................................................................................... 124
Larger Memory Systems ..................................................................................................................... 124
ECC............................................................................................................................................................ 125
SDRAM Timing ......................................................................................................................................... 125
SDRAM Refresh........................................................................................................................................ 126
SDRAM Initialization and Commands .................................................................................................... 126
I/O Control................................................................................................................................................. 128
Timing Parameter Guidelines ................................................................................................................. 131
Performance Monitoring Features.......................................................................................................... 134
ZBbus Monitoring .................................................................................................................................... 134
Configuration Registers .......................................................................................................................... 135
Section 7: DMA.................................................................................................................147
DMA Controllers ....................................................................................................................................... 147
Data Buffers and Descriptors ................................................................................................................. 147
Document 1250_1125-UM100CB-R
B roa dcom Co rpo rat ion
BCM1250/BCM1125/BCM1125H
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