Cacheable Access Blocking; Generic Bus Parity - Broadcom BCM1250 User Manual

User Manual
10/21/02
C
ACHEABLE
To provide protection against programming errors and prevent side effects from accidental speculative
accesses through kseg0 and xkphys (see section
cacheable reads may be blocked from being driven on the generic bus. This is done by setting the blk_cache
bit in the io_ext_start_addr register. If this bit is set and a cacheable access is done to the region then the
access will be blocked. This bit is clear by default and should be left clear for memory areas like the boot ROM
that are likely to be cached for performance. To avoid causing the CPU to take an imprecise error as the result
of a bad speculative access, a data error is not raised when a read is blocked. The access is just logged.
When a cacheable access is blocked:
1 No cycle is run on the generic bus.
2 For a read UNPREDICTABLE data is returned, marked with the valid data return code.
3 The io_cacheable_blk bit in the io_interrupt_status register is set (but no interrupt is raised). This bit is
cleared by a read of the register.
4 If the log is not locked (i.e. the io_error interrupt is deasserted) the address of the access gets logged in
io_interrupt_addr0 and io_interrupt_addr1.
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ENERIC US
A reset time system configuration option enables parity on the data portion of a transfer on the generic bus (not
the address). This is provided on the IO_ADP[3:0] pins, which are available as GPIO pins if generic bus parity
is disabled. If parity is enabled for the system then each region can be configured in the io_ext_cfg register to
have even, odd or no parity check.
On read transactions from parity generating devices, the parity bit of each byte of the incoming data is latched
at the same time as the data, and checked against the parity computed for the byte. If an error is detected,
then the address and region of the error are logged, the io_rd_par_int bit is set in the io_interrupt_status
register, the generic bus error interrupt is raised and the data is passed to the system bus marked with a bus
error. The data must be passed to the system bus to terminate the read transaction, the error flag will prevent
its use. The Bus Watcher in the SCD (see section
and increment the bus_io_error count. If the data is returning to one of the CPUs then the bus error exception
will be raised (thus the CPU could be told about the error three times: the bus error exception, the bus watcher
error interrupt and the interrupt from the generic bus controller).
When parity is enabled for a region it will be generated for the data in writes and will be driven on the parity
pins with the same timing that the data has. If the device sees a parity error on writes it is device dependent
how it responds and how it reports the error.
the byte lanes.
Data with an uncorrectable error from the system bus will not be seen by the generic bus interface. The Bus
Watcher will log and report the error.
Document 1250_1125-UM100CB-R
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CCESS LOCKING
P
ARITY
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Section: "CPU Speculative Execution" on page
Section: "Bus Watcher" on page
Table 247 on page 363 shows how the IO_ADP pins match with
64) will note the error flag
Section 11: Generic/Boot Bus Page
16)
363