Table 96: Current Descriptor A Debug Register; Table 97: Current Descriptor B Debug Register; Table 98: Current Descriptor Address Register - Broadcom BCM1250 User Manual

User Manual
10/21/02
dma_cur_dscr_a_mac_0_rx_ch_0-00_1006_4820 dma_cur_dscr_a_mac_0_tx_ch_0-00_1006_4C20
dma_cur_dscr_a_mac_0_rx_ch_1-00_1006_4920 dma_cur_dscr_a_mac_0_tx_ch_1-00_1006_4D20
dma_cur_dscr_a_mac_1_rx_ch_0-00_1006_5820 dma_cur_dscr_a_mac_1_tx_ch_0-00_1006_5C20
dma_cur_dscr_a_mac_1_rx_ch_1-00_1006_5920 dma_cur_dscr_a_mac_1_tx_ch_1-00_1006_5D20
dma_cur_dscr_a_mac_2_rx_ch_0-00_1006_6820 dma_cur_dscr_a_mac_2_tx_ch_0-00_1006_6C20
dma_cur_dscr_a_mac_2_rx_ch_1-00_1006_6920 dma_cur_dscr_a_mac_2_tx_ch_1-00_1006_6D20
dma_cur_dscr_a_ser_0_rx - 00_1006_0420
dma_cur_dscr_a_ser_1_rx - 00_1006_0820
Bits Name Default
63:0 cur_a 64'b0
dma_cur_dscr_b_mac_0_rx_ch_0-00_1006_4828 dma_cur_dscr_b_mac_0_tx_ch_0-00_1006_4C28
dma_cur_dscr_b_mac_0_rx_ch_1-00_1006_4928 dma_cur_dscr_b_mac_0_tx_ch_1-00_1006_4D28
dma_cur_dscr_b_mac_1_rx_ch_0-00_1006_5828 dma_cur_dscr_b_mac_1_tx_ch_0-00_1006_5C28
dma_cur_dscr_b_mac_1_rx_ch_1-00_1006_5928 dma_cur_dscr_b_mac_1_tx_ch_1-00_1006_5D28
dma_cur_dscr_b_mac_2_rx_ch_0-00_1006_6828 dma_cur_dscr_b_mac_2_tx_ch_0-00_1006_6C28
dma_cur_dscr_b_mac_2_rx_ch_1-00_1006_6928 dma_cur_dscr_b_mac_2_tx_ch_1-00_1006_6D28
dma_cur_dscr_b_ser_0_rx - 00_1006_0428
dma_cur_dscr_b_ser_1_rx - 00_1006_0828
Bits Name Default
63:0 cur_b 64'b0
dma_cur_daddr_mac_0_rx_ch_0 - 00_1006_4830
dma_cur_daddr_mac_0_rx_ch_1 - 00_1006_4930
dma_cur_daddr_mac_1_rx_ch_0 - 00_1006_5830
dma_cur_daddr_mac_1_rx_ch_1 - 00_1006_5930
dma_cur_daddr_mac_2_rx_ch_0 - 00_1006_6830
dma_cur_daddr_mac_2_rx_ch_1 - 00_1006_6930
dma_cur_daddr_ser_0_rx - 00_1006_0430
dma_cur_daddr_ser_1_rx - 00_1006_0830
Bits Name
39:0 dscr_addr
55:40 count
Document 1250_1125-UM100CB-R

Table 96: Current Descriptor A Debug Register

READ ONLY
The current descriptor first double word can be read from this register (intended for
debugging only).

Table 97: Current Descriptor B Debug Register

READ ONLY
The current descriptor second double word can be read from this register (intended for
debugging only).

Table 98: Current Descriptor Address Register

READ ONLY
Default
40'b0 The current descriptor address can be read from this field.
If count is nonzero the address is the descriptor being used.
If count is zero the address is where the next descriptor will be fetched from.
16'b0 The current count of descriptors owned by the DMA engine can be read from
this field. (It provides the same information as reading the dma_dscr_count
register).
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
dma_cur_dscr_a_ser_0_tx - 00_1006_04A0
dma_cur_dscr_a_ser_1_tx - 00_1006_08A0
Description
dma_cur_dscr_b_ser_0_tx - 00_1006_04A8
dma_cur_dscr_b_ser_1_tx - 00_1006_08A8
Description
dma_cur_daddr_mac_0_tx_ch_0 - 00_1006_4C30
dma_cur_daddr_mac_0_tx_ch_1 - 00_1006_4D30
dma_cur_daddr_mac_1_tx_ch_0 - 00_1006_5C30
dma_cur_daddr_mac_1_tx_ch_1 - 00_1006_5D30
dma_cur_daddr_mac_2_tx_ch_0 - 00_1006_6C30
dma_cur_daddr_mac_2_tx_ch_1 - 00_1006_6D30
dma_cur_daddr_ser_0_tx - 00_1006_04B0
dma_cur_daddr_ser_1_tx - 00_1006_08B0
Description
Section 7: DMA Page 167