Broadcom BCM1250 User Manual page 11

User Manual
10/21/02
8-Bit EOP Flagged Packet FIFO ......................................................................................................... 298
16-Bit Packet FIFO Operation ................................................................................................................. 299
16-Bit GMII Style Packet FIFO............................................................................................................ 299
16-Bit Encoded Packet FIFO .............................................................................................................. 300
Restrictions When Resetting the Interface ............................................................................................ 301
MAC Registers.......................................................................................................................................... 302
Section 10: Serial Interfaces ........................................................................................... 321
Introduction .............................................................................................................................................. 321
Asynchronous Mode................................................................................................................................ 322
Baud Rate Generators ............................................................................................................................. 322
Operation .................................................................................................................................................. 323
Interrupts .................................................................................................................................................. 325
Loopback .................................................................................................................................................. 326
DUART Registers ..................................................................................................................................... 327
Synchronous Mode .................................................................................................................................. 337
Functional Overview ........................................................................................................................... 337
Input Line Interface ............................................................................................................................. 340
Input Using an External Enable ................................................................................................... 340
Input Using the Internal Sequencer ............................................................................................. 341
Output Line Interface .......................................................................................................................... 342
Output Using an External Enable ................................................................................................ 342
Output Using the Internal Sequencer .......................................................................................... 343
Synchronous Serial Protocol Engine ..................................................................................................... 344
Operation in HDLC Mode.................................................................................................................... 344
Framing Parameters .................................................................................................................... 345
HDLC Transmitter ........................................................................................................................ 345
HDLC Receiver ............................................................................................................................ 347
Operation in Transparent Mode .......................................................................................................... 349
Transmitter in Transparent Mode ................................................................................................ 350
Receiver in Transparent Mode .................................................................................................... 350
Synchronous Interface Configuration.................................................................................................... 351
DMA Configuration.............................................................................................................................. 351
FIFO Configuration ............................................................................................................................. 351
Protocol Engine Configuration ............................................................................................................ 351
Document 1250_1125-UM100CB-R
B roa dcom Co rpo rat ion
BCM1250/BCM1125/BCM1125H
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