Fixed Cycle Write Access; Figure 75: Fixed Cycle Write Access - Broadcom BCM1250 User Manual

User Manual
10/21/02
F C
IXED YCLE
clk100
io_ale
io_ad[23:0]
io_ad[31:24]
io_ad[31:0]
io_adp[3:0]
io_cs_l[n]
io_oe_l
io_wr_l
io_rdy
The fixed cycle write is the same as the fixed cycle read, except IO_OE_L remains deasserted and the
ale_to_wr and wr_width parameters are used to set the assertion of the IO_WR_L signal. The data is output
on the IO_AD lines with the assertion of chip select.
Document 1250_1125-UM100CB-R
W A
RITE CCESS
ale_width
Address
ale_to_cs

Figure 75: Fixed Cycle Write Access

B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Address
Data
Data
Parity
cs_width
ale_to_wr wr_width
idle_cycle
Non Muxed
Muxed
1 cycle
Section 11: Generic/Boot Bus Page 367