Table 241: Serial Status Debug Register; Table 242: Serial Interrupt Mask Register - Broadcom BCM1250 User Manual

User Manual
10/21/02
Bits Name
18 rx_eop_seen
19 rx_hwm
20 rx_lwm
21 rx_dscr
22 rx_derr
23 reserved
24 tx_eop_count
25 tx_eop_timer
26 tx_eop_seen
27 tx_hwm
28 tx_lwm
29 tx_dscr
30 tx_derr
31 tx_dzero
63:32 notimp
Bits Name Default
31:0 status 32'b0
63:32 notimp 32'bx
Bits Name Default
31:0 mask 32'b0
63:32 notimp 32'bx
Document 1250_1125-UM100CB-R
Table 240: Synchronous Serial Status Register
ser_status_0 - 00_1006_0588
ser_status_1 - 00_1006_0988
READ ONLY, Read Clears
Set at the end of any packet transfer. It can be used during polling to determine if any
packets have been transferred since the register was read (regardless of the setting of
the int_pktcnt field).
Set if the high watermark interrupt is raised.
Set if the low watermark interrupt is raised.
Set if the interrupt is triggered by a descriptor with the interrupt on packet end command.
Set if the controller ran out of descriptors during a packet reception. The channel will be
stopped. Software must disable and re-enable the channel to clear this fault.
Reserved
Set if the EOP interrupt was raised as a result of the packet count being reached.
Set if the EOP interrupt was raised as a result of the packet timer triggered.
Set at the end of any packet transfer. It can be used during polling to determine if any
packets have been transferred since the register was read (regardless of the setting of
the int_pktcnt field).
Set if the high watermark interrupt is raised.
Set if the low watermark interrupt is raised.
Set if the interrupt is triggered by a descriptor with the interrupt on packet end command.
Set if the controller ran out of descriptors during a packet transmission. The channel will
be stopped. Software must disable and re-enable the channel to clear this fault.
Set if a descriptor has a packet length of zero. The channel will be stopped. Software
must disable and re-enable the channel to clear this fault.
Not implemented.

Table 241: Serial Status Debug Register

ser_status_debug_0 - 00_1006_05A8
ser_status_debug_1 - 00_1006_09A8
Reading this register gives the same value as reading the ser_status register, but does
not have the side effect of clearing the register.
Not implemented.

Table 242: Serial Interrupt Mask Register

ser_int_mask_0 - 00_1006_0590
ser_int_mask_1 - 00_1006_0990
Setting a bit in this register enables generation of an interrupt when the corresponding
status bit is set in the ser_status register.
Not implemented.
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
(Cont.)
Description
Description
Description
Section 10: Serial Interfaces Page 357