Table 32: System Performance Counters; Table 33: System Performance Counter Sources - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
Table 31: System Performance Counter Configuration Registers
Bits Name
31:24 Counter 3 source
32 clear
33 enable
63:34 reserved
Bits Name
39:0 Count
40 oflow
63:41 reserved
Value
00 No count.
01 Bus cycles are counted. The counter is incremented each ZBbus clock cycle (half the CPU clock).
02 Bus cycles used. The counter is incremented every cycle the address portion of ZBbus is used.
03 Address bus cycles waiting grant. The counter is incremented every cycle some agent loses arbitration for the
address bus (i.e. there are two or more requesters in arbitration).
04 Address bus cycles arbitrated but not used. The counter is incremented every time the address bus is granted
but the agent drives a NOP command.
05 Address match 0 count - counts each bus address cycle that matches the address trap comparator. The
occurrence counter (that is used to determine if the address trap should interrupt) is ignored, the performance
counter will increase every cycle there is a hit in the trap.
06 Address match 1 count. (See comments for Address match 0.)
07 Address match 2 count. (See comments for Address match 0.)
08 Address match 3 count. (See comments for Address match 0.)
09 Data bus cycles waiting grant. The counter is incremented every cycle some agent loses arbitration for the data
bus (i.e. there are two or more requesters in arbitration).
0A Data bus cycles arbitrated but not used. The counter is incremented every time the data bus is granted but the
agent drives a NOP command.
0B CPU0 EDEN. The counter is incremented every time CPU 0 asserts its External Debug Event Notification (EDEN)
signal. This can be asserted by software, or watchpoint register hits.
0C CPU1 EDEN. The counter is incremented every time CPU 1 asserts its External Debug Event Notification (EDEN)
signal. This can be asserted by software, or watchpoint register hits.
Page 62 Section 4: System Control and Debug Unit
perf_cnt_cfg - 00_1002_04C0
Default
8'b0 Sets the source for counter 3.
1'b0 If this bit is set in a write to the register the counters will be reset, the bit
self-clears and always reads as zero.
1'b0 Set to enable the counters, clear to stop them. Cleared automatically by
any counter reaching its maximum count.
30'b0 Reserved

Table 32: System Performance Counters

perf_cnt_0 - 00_1002_04D0
perf_cnt_1 - 00_1002_04D8
perf_cnt_2 - 00_1002_04E0
perf_cnt_3 - 00_1002_04E8
Default
40'bx Performance counter.
1'b0 This bit is set if the counter overflows.
23'b0 Reserved

Table 33: System Performance Counter Sources

Condition Counted
B r oadco m C orp or ati on
(Cont.)
Description
Description
Document 1250_1125-UM100CB-R
User Manual
10/21/02