Broadcom BCM1250 User Manual page 27

User Manual BCM1250/BCM1125/BCM1125H
10/21/02
Table 278: GPIO Read Register.................................................................................................................... 399
Table 279: GPIO Input Invert Control Register.............................................................................................. 399
Table 280: GPIO Glitch Filter Select Register ............................................................................................... 400
Table 281: GPIO Direction Register .............................................................................................................. 400
Table 282: GPIO Pin Clear Register ............................................................................................................. 400
Table 283: GPIO Pin Set Register................................................................................................................. 400
Table 284: Other Pins that can be Used as General Inputs or Outputs ........................................................ 401
Table 285: Supported SMBus Transfer Types .............................................................................................. 406
Table 286: Command/Address Options ........................................................................................................ 408
Table 287: Write Data Options ...................................................................................................................... 408
Table 288: Read Data Options ...................................................................................................................... 409
Table 289: SMBus Clock Frequency Registers ............................................................................................. 416
Table 290: SMBus Command Registers ....................................................................................................... 416
Table 291: SMBus Control Registers ............................................................................................................ 416
Table 292: SMBus Status Registers.............................................................................................................. 417
Table 293: SMBus Data Registers ................................................................................................................ 417
Table 294: SMBus Extra Data Registers....................................................................................................... 417
Table 295: SMBus Packet Error Check Registers......................................................................................... 418
Table 296: SMBus Start and Command Registers SMBus Mode ................................................................. 418
Table 297: SMBus Start and Command Registers Extended Mode ............................................................. 419
Table 298: JTAG Signals............................................................................................................................... 422
Table 299: JTAG Instructions ........................................................................................................................ 424
Table 300: JTAG Device ID Register ............................................................................................................ 425
Table 301: JTAG Wafer ID Register.............................................................................................................. 426
Table 302: System Control Scan Chain ........................................................................................................ 428
Table 303: Performance Counter Scan Chain............................................................................................... 430
Table 304: Trace Control Scan Chain ........................................................................................................... 431
Table 305: Trace Current Count Scan Chain ................................................................................................ 431
Table 306: Ring Oscillator Scan Chain.......................................................................................................... 432
Table 307: CPU and Probe Accesses ........................................................................................................... 436
Table 308: JTAG Address Register Scan Chain ........................................................................................... 439
Table 309: Data Register Scan Chain ........................................................................................................... 439
Table 310: EJTAG Control Register .............................................................................................................. 440
Table 311: Internal Register Addresses by Function..................................................................................... 446
Table 312: Internal Registers Ordered by Address ....................................................................................... 464
B roa dcom Co rpo rat ion
Document 1250_1125-UM100CB-R Page xxvii