Broadcom BCM1250 User Manual page 23

User Manual BCM1250/BCM1125/BCM1125H
10/21/02
Table 138: PCI Adaptive Extend Register - Offset 98 Bits [31:0] .................................................................. 243
Table 139: PCI Bypass Control Register - RevId >= 3 Offset A8 Bits [31:0] ................................................. 244
Table 140: HyperTransport Configuration Header (Type 1) .......................................................................... 245
Table 141: HyperTransport Bridge Command Register - Offset 4 Bits [15:0] ............................................... 247
Table 142: HyperTransport Bridge Primary (ZBbus) Status Register - Offset 4 Bits [31:16]......................... 248
Table 143: HyperTransport Bridge Secondary (HT) Status Register - Offset 1C Bits [31:16]....................... 248
Table 144: HyperTransport Bridge Control Register - Offset 3C Bits [31:16] ................................................ 249
Table 145: HyperTransport Command Register - Offset 40 Bits [31:16]....................................................... 249
Table 146: HyperTransport Link Control Register - Offset 44 Bits [15:0] ...................................................... 250
Table 147: HyperTransport Link Configuration Register - Offset 44 Bits [31:16] .......................................... 251
Table 148: HyperTransport Link Frequency Register - Offset 48 Bits [15:8]................................................. 251
Table 149: HyperTransport SRI Command Register - Offset 50 Bits [31:16] ................................................ 252
Table 150: HyperTransport Isochronous BAR - Offset 5C Bits [31:0] ........................................................... 252
Table 151: HyperTransport Isochronous Ignore Mask - Offset 60Bits [31:0] ................................................ 253
Table 152: HyperTransport Error Control Register - Offset 68 Bits [23:0]..................................................... 253
Table 153: HyperTransport Error Status Register - Offset 68 Bits [31:24] .................................................... 254
Table 154: HyperTransport SRI Transmit Control Register - Offset 6C Bits [23:16] ..................................... 254
Table 155: HyperTransport SRI Data Buffer Allocation Register - Offset 6C Bits [15:0] ............................... 254
Table 156: HyperTransport Additional Status Register - Offset 70 ............................................................... 255
Table 157: HyperTransport SRI Transmit Buffer Count Max Register - Offset C8 Bits [31:0]....................... 255
Table 158: HyperTransport Diagnostic Receive CRC Expected - Offset DC ................................................ 255
Table 159: HyperTransport Diagnostic Receive CRC Received - Offset F0 ................................................. 255
Table 160: Ethernet Frame Fields ................................................................................................................. 269
Table 161: Transmission Error Conditions .................................................................................................... 273
Table 162: Receiver Error Conditions ........................................................................................................... 276
Table 163: Ethernet Type Mappings ............................................................................................................. 282
Table 164: Back Pressure Methods in Half-Duplex Operation ...................................................................... 284
Table 165: Pause Frame Options.................................................................................................................. 285
Table 166: MAC to PHY Management Protocol ............................................................................................ 289
Table 167: RMON Counters .......................................................................................................................... 289
Table 168: BCM1125 Ethernet/Fifo Pin Usage ............................................................................................. 292
Table 169: BCM1250 Ethernet/Fifo Pin Usage ............................................................................................. 293
Table 170: Codes for GMII Packet FIFO Mode ............................................................................................. 295
Table 171: Codes for 8-Bit Encoded Bypass Mode....................................................................................... 296
Table 172: Codes for 8-Bit SOP Packet FIFO............................................................................................... 297
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