Broadcom BCM1250 User Manual page 106

BCM1250/BCM1125/BCM1125H
Bits Field
63:60 A_DW
65:64 A_L1CA
68:66 A_CMD
103:69 A_AD[39:5]
113:104 A_ID[9:0]
125:114 COUNT
126 DTRIG
127 ATRIG
The data trace consists of two 128 bit entries. The first contains bits [255:128] from the databus, the second
has bits [127:0].
Page 78 Section 4: System Control and Debug Unit
Table 49: Trace Buffer Address/Control Bundle
Encoded byte enables. Indicates any doublewords with valid bytes.
DW[n=3:0] = A_BE[8*n + 0] | A_BE[8*n + 1] | A_BE[8*n + 2] | A_BE[8*n + 3] |
A_BE[8*n + 4] | A_BE[8*n + 5] | A_BE[8*n + 6] | A_BE[8*n + 7]
If only one doubleword is set then the BYT field indicates the valid bytes, if more than one
doubleword is set then knowledge of the transaction will be needed. Other than uncached
accelerated writes, all CPU transactions will be within a single doubleword or of the full
cacheline.
L1 cacheablility bits.
00: Cacheable non-coherent.
01: Cacheable coherent.
10: Uncacheable.
11: Uncacheable (accelerated, may have merged writes).
Address phase command bits
000: READ_SHD.
001: READ_EXC.
010: WRITE.
011: WRITE and INVALIDATE.
100: INVALIDATE.
101-110: Reserved
111: No command valid. (NOP)
Line address of the transaction on the bus.
This is the value of the address ID bits on the bus.
A_ID[9:6] - Requester ID.
A_ID[5:0] - Unique number within granted requester.
This is the number of bus cycles between the last traced entry and this entry. This is a 12 bit
saturating counter. If two samples are captured on consecutive cycles the count will be zero.
The count is set to zero when the trace buffer is reset.
This bit is set when a sequence completing with Dsample caused this control entry to be
traced. The next 256 bits contains the data bits [255:0].
This bit is set when a sequence completing with Asample caused this control entry to be
traced.
B r oadco m C orp or ati on
(Cont.)
Description
Document
User Manual
10/21/02
1250_1125-UM100CB-R