Broadcom BCM1250 User Manual page 416

BCM1250/BCM1125/BCM1125H
Mode Input signals from
Control Bits
0 1
0 1
0 1
0 0
0 0
O PCMCIA S
THER
The Memory Only PCMCIA slot includes two signals for indicating the status of a battery on the card (BVD1
and BVD2). If these are required they can be connected via a level translating buffer to GPIO pins configured
as inputs.
An additional signal WAIT# is used on some cards to indicate that it needs to extend the access time to a
transaction. This can be connected through a buffer (to protect the interface input from 5V PCMCIA cards) to
the generic bus IO_RDY input. Additional logic may be required to combine the signal with the ready or busy
signals from other devices if other generic bus chip select regions use the acknowledgement based mode. If
the WAIT# line is connected in this way and a card that does not support WAIT# is inserted, the interface can
be switched to fixed timing mode to ignore the IO_RDY signal and allow the card to be used.
The I/O and Memory PCMCIA interface changes the use of some of the signals and adds some others.
• The READY pin becomes IREQ#, an active low interrupt signal. This will work with the standard
connection to PC_READY, and the PCMCIA interrupt can be raised whenever the pin changes state
regardless of it indicating the card is ready, or is interrupting.
• The WP pin becomes IOIS16#. This is used by the card to inform the host for a particular address if a 16
bit access is possible. The generic bus does not support this behavior, so for cards which need this
(indicated in the TPCE_IO field of the CISTPL_CFTABLE_ENTRY configuration tuple) either the interface
must be configured for 8 bit only operations or a software restriction made to ensure only 8 bit accesses
are done to registers that are 8 bits. The PCMCIA specification indicates that on any card that has a
mixture of 8 and 16 bit registers byte registers that are at an odd address can be read on the D[15:8] byte
lane when CE2# is asserted, matching
• The IORD# and IOWR# signals have been added. These match OE# and WE# but for accesses to I/O
addresses. One method of generating these is with external logic that drives IO_OE_L and IO_WE_L to
either (OE#, WE#) or (IORD#, IOWR#) based on an address bit.
• The PCMCIA card does not share the generic bus region with other peripherals, so the input port
acknowledgement signal INPACK# is not needed.
• BVD2 is replaced by SPKR#, which can be used to drive a beep speaker. This would go to some other
block than the BCM1250 or BCM1125/H.
• BVD1 is replaced by STSCHNG# which is used to indicate the card status has changed and the card pin
replacement register should be read to get the values that would otherwise be reported on the READY,
WP, BVD1 or BVD2 pins.
Page 388 Section 12: PCMCIA Control Interface
Table 270: PCMCIA VPP Power Enable Truth Table
Software
PCMCIA card Control
X 1 X X
0 0 X 0
0 0 X 1
X X X 0
X X X 1
IGNALS
B r oadco m C orp or ati on
Card State
Non-PCMCIA, cd used, forced off
Non-PCMCIA, cd used, sw turned off
Non-PCMCIA, cd used, sw turned on
Non-PCMCIA, sw turned off
Non-PCMCIA, sw turned on
Table 270 on page 388.
User Manual
(Cont.)
Document 1250_1125-UM100CB-R
10/21/02
Power
Output
0
0
1
0
1