Standard Management Mode Accesses (Both Ecc_Diag Address Bits Zero) - Broadcom BCM1250 User Manual

User Manual
10/21/02
S M
TANDARD
Standard management mode accesses are any made to the management address range with the ECC_diag
address bits clear.
Management reads will return the line from the addressed index and way. The normal ECC checking and
correction is performed. Data with correctable ECC errors will be returned with the errors corrected, flagged
as ECC corrected. Data with uncorrectable errors will be flagged with the uncorrectable data ECC error code.
Similarly, if the tag has a correctable ECC error it will be corrected and the data returned with the tag ECC
corrected flag, and if the tag has an uncorrectable ECC error data is returned with the uncorrectable tag error
code.
As the management read is done the tag associated with the entry is transferred to the l2_read_tag register.
This register will contain the tag after ECC correction and the raw tag ECC bits. The register can be read by
the CPU with an uncacheable read. If cacheable reads are used for the management read that gets the data
care is required since the CPU implements run-under-miss and there is no ordering guaranteed between
cacheable and uncacheable reads. The ordering can be forced by the CPU performing a SYNC or an ALU
operation on the data read from the cache management access (e.g. add zero) before reading the tag register.
There is no ordering problem if the management access is done using an uncacheable read because the CPU
will maintain the order between the management access and the l2_read_tag register, but uncached access
is less efficient if all the data in the line needs to be examined.
Management writes will write the data to the addressed index and way. The data is written with correct ECC
bits. The previous data in the addressed cache line will be lost, evicts are never done. If the previous data had
an ECC error this will not be reported. A new cache tag (with correct ECC) is written, tagging the line with the
address used in the write (the bits put in the tag are shown in
of the tag are copied from bits 20 and 19 of the address.
The L2 cache can be invalidated by doing standard management writes to each index and way of the cache
using an address that causes the tag to be written with the valid bit clear. In addition to invalidating the cache
this will cause correct ECC to be written to all the cache blocks and tags, so there will not be spurious ECC
errors on the first use of a cache line. This must be done during system startup before the cache can be used.
ECC error recovery code should not directly read the erroneous data from the cache. If the data contains an
uncorrectable error it will still be signalled as such, so the CPU would see it as a cache error. However the bus
watcher in the SCD logs the data whenever an uncorrectable error is reported, and the L2 controller logs the
address and tag (with the error) in the l2_ecc_tag register.
Document 1250_1125-UM100CB-R
M A
ANAGEMENT ODE
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
( ECC_
CCESSES BOTH
Figure 13 on page
DIAG ADDRESS BITS ZERO
95). The valid and dirty bits
Section 5: L2 Cache
)
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