Table 264: Output Drive Control Register 0 - Broadcom BCM1250 User Manual

User Manual
10/21/02
Bits Name
13:12 reserved
15:14 io_drv_D 2'b01 8mA
63:16 notimp
Bits Name Default
1:0 reserved
3:2 io_drv_E
5:4 reserved
7:6 io_drv_F
9:8 reserved
11:10 io_drv_G
13:12 reserved
15:14 io_drv_H
63:16 notimp
Document 1250_1125-UM100CB-R

Table 264: Output Drive Control Register 0

io_drive_0 - 00_1006_1300
A write to any bit causes all bits to be written.
Default
2'b11 Reserved
Group D drive strength control. High drive 6/8/10/12 mA. Uses Slew0.
PC_EN3V PC_EV5V PC_ENVPP GPIO[15:12].
48'bx Not implemented.
Table 265: Output Drive Control Register 1
io_drive_1 - 00_1006_1308
A write to any bit causes all bits to be written.
2'b11 Reserved
2'b01 8 Group E drive strength control. High drive 6/8/10/12 mA. Uses Slew0.
mA GPIO[11:6], GPIO[1:0].
2'b11 Reserved
2'b01 8 Group F drive strength control. High drive 6/8/10/12 mA. Uses Slew0.
mA GPIO[5:2]/IO_ADP[3:0].
2'b11 Reserved
2'b01 Group G drive strength control. Low drive 2/4/6/8mA. Uses Slew0.
4 mA SDA0 SCL0.
2'b11 Reserved
2'b01 Group H drive strength control. Low drive 2/4/6/8mA. Uses Slew0.
4 mA SDA1 SCL1.
48'bx Not implemented.
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
(Cont.)
Description
Description
Section 11: Generic/Boot Bus Page 379