Broadcom BCM1250 User Manual page 21

User Manual BCM1250/BCM1125/BCM1125H
10/21/02
Table 68: Supported SDRAMs ...................................................................................................................... 123
Table 69: Commands that can be Issued Through mc_dramcmd Register .................................................. 126
Table 70: Adjustment Percentages and Multiplier for Values of DLL M ........................................................ 128
Table 71: First DQS Window Opening and Closing (Typical)........................................................................ 132
Table 72: Memory Channel Configuration Register on BCM1250 ................................................................ 135
Table 73: Memory Channel Configuration Register on BCM1125/H............................................................. 136
Table 74: Memory Clock Configuration Register ........................................................................................... 138
Table 75: DRAM Command Register ............................................................................................................ 139
Table 76: DRAM Mode Register.................................................................................................................... 139
Table 77: SDRAM Timing Register ............................................................................................................... 140
Table 78: SDRAM Timing Register 2 ............................................................................................................ 141
Table 79: Chip Select Start Address Register ............................................................................................... 141
Table 80: Chip Select End Address Register ................................................................................................ 141
Table 81: Chip Select Interleave Register ..................................................................................................... 142
Table 82: Row Address Bits Select Register................................................................................................. 142
Table 83: Column Address Bits Select Register............................................................................................ 142
Table 84: Bank Address Bits Select Register................................................................................................ 143
Table 85: Chip Select Attribute Register ....................................................................................................... 143
Table 86: ECC Test Data Register ................................................................................................................ 144
Table 87: ECC Test ECC Register ................................................................................................................ 144
Table 88: Data Buffer Parameters................................................................................................................. 148
Table 89: Data Parameters ........................................................................................................................... 148
Table 90: Address Used for ASIC Mode Transfers ....................................................................................... 160
Table 91: Ethernet and Serial DMA Configuration Register 0 ....................................................................... 163
Table 92: Ethernet and Serial DMA Configuration Register 1 ....................................................................... 164
Table 93: Ethernet and Serial DMA Descriptor Base Address Register........................................................ 166
Table 94: ASIC Mode Base Address............................................................................................................. 166
Table 95: Descriptor Count Register ............................................................................................................. 166
Table 96: Current Descriptor A Debug Register ............................................................................................ 167
Table 97: Current Descriptor B Debug Register ............................................................................................ 167
Table 98: Current Descriptor Address Register............................................................................................. 167
Table 99: Ethernet Receive Packet Drop Registers (Only if System Revision >= PERIPH_REV3).............. 168
Table 100: DMA Descriptor First Doubleword ............................................................................................... 169
Table 101: DMA Descriptor Second Doubleword.......................................................................................... 169
Table 102: Unaligned Buffer Format DMA Descriptor First Doubleword....................................................... 170
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