Memory Mapped Devices; Hypertransport Expansion Space; Configuration Space - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
M M
EMORY APPED
There is a 512MB region for mapping memory mapped PCI and HyperTransport devices. Logically this all
maps to the PCI and a segment of it is bridged to the HyperTransport. (On the BCM1125 there is no
HyperTransport interface and all accesses to this space are PCI accesses.) Thus the area is divided up into
the three regions A, B and C in the address map. Region A contains all the devices on the PCI bus (including
bridges) that the configuration code allocated before the HyperTransport bridge. Region B contains the
addresses bridged to the HyperTransport fabric, accesses to this address range are detected by the I/O Bridge
0 and sent to the HyperTransport controller directly. Region C consists of the address range allocated to
devices on the PCI bus that were configured after the HyperTransport bridge and empty space that was not
allocated. When the part is running in big endian mode this area of memory accesses the PCI and
HyperTransport using the match byte lane policy.
Region D (offset from the main area by setting address bit 29) is directly mapped onto the A, B and C regions,
but uses the match bit lane policy.
H T
YPER RANSPORT
There is a large region of the address space allocated to HyperTransport expansion. This is marked as region
N in the address map above
area requires the use of full 40 bit physical addresses. Configuration software will also need modification to
use this area (by default it will attempt to put all HyperTransport peripherals in region B since they will seem to
be bridged from the PCI bus). The endian policy used in the expansion space is determined by the exp_endian
bit in the SRI Command Register. If this bit is clear then all of the expansion space will use the match byte lane
policy. If the bit is set then address bit [38] is used to select the endian policy and the address bit is cleared as
the request passes through the bridge. Thus:
• exp_endian bit clear:
- 80_0000_0000 - F7_FFFF_FFFF use the match bytes policy.
• exp_endian bit set:
- 80_0000_0000 - BF_FFFF_FFFF and E0_0000_0000 - F7-FFFF-FFFF use the match bytes
policy.
- C0_0000_0000 - DF_FFFF_FFFF map to 80_0000_0000 - 9F_FFFF_FFFF and use the match bits
policy.
C
ONFIGURATION
Configuration cycles can be performed on the PCI bus and HyperTransport fabric by accessing the
configuration space. Again, with address bit [29] clear the match byte lane policy is used and with a[29] set the
match bit lane policy is selected. See
full discussion of configuration.
Page 194 Section 8: PCI Bus and HyperTransport Fabric
D
EVICES
E S
XPANSION PACE
(Figure 37 on page
S
PACE
Section: "Configuration of PCI and HyperTransport" on page 234
B r oadco m C orp or ati on
193). This space is Reserved on the BCM1125. Use of this
User Manual
10/21/02
Document 1250_1125-UM100CB-R
for a