Figure 54: Transmit Fifo Thresholds - Broadcom BCM1250 User Manual

User Manual
10/21/02
T O
RANSMITTER
T
RANSMITTER
The transmitter clock is accepted as an input from the PHY device for 10/100 Mbit/s operation. However, for 1
Gbit/s operation the data lines are clocked at 125 MHz so the clock is forwarded with the data. In this case the
reference clock input is used (on the BCM1250, the REFCK01 pin is for interfaces E0 and E1, and the REFCK2
pin for interface E2; on the BCM1125/H, REFCK0 is for E0 and REFCK1 for E1). The clock source is
configured by the MAC speed selection in the mac_cfg register.
The transmit FIFO is a 64 bit wide fifo with 128 entries.
configure it. When the FIFO has space for data it will signal the DMA engine to request data. The tx_wr_thrsh
field in the mac_thrsh_cfg sets the number of empty entries there must be in the FIFO before it will request
data. The DMA engine fetches either 32 bytes or 64 bytes at a time, so this value should be set to 4 or 8.
The data from the transmit FIFO is read out by the protocol engine for transmission. Once transmission of a
packet has started the DMA engine must ensure that there is always data in the FIFO when the protocol engine
needs it. If the FIFO is empty at any time before the end of the packet then an underflow error is reported and
transmission fails (in encoded Packet FIFO mode the transmission will not fail, instead cycles with no valid data
will be inserted in the link protocol). To reduce the likelihood of the FIFO becoming empty the tx_rd_thrsh
threshold can be set to ensure a certain number of entries have been written to the FIFO before transmission
starts.
64 bit wide
Document 1250_1125-UM100CB-R
PERATION
C
ONFIGURATION
Start of
Packet
S
O
P
tx_rd_thrsh
tx_rl_thrsh
FIFO must be filled to here
before SOP will be sent

Figure 54: Transmit FIFO Thresholds

B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Figure 54 shows the thresholds that are used to
Errors that happen between
SOP and this entry can be
automatically retried
tx_wr_thrsh
The FIFO will request
data if at least this
much is empty
Section 9: Ethernet MACs Page 271