Broadcom BCM1250 User Manual page 6

BCM1250/BCM1125/BCM1125H
System Control ...........................................................................................................................................41
Mailbox Registers .......................................................................................................................................46
Interrupts .....................................................................................................................................................47
HyperTransport Interrupts .....................................................................................................................48
The Full Interrupt Mapper ......................................................................................................................50
Timers ..........................................................................................................................................................57
Watchdog Timers ..................................................................................................................................57
General Timers......................................................................................................................................58
Timer Special Cases .............................................................................................................................58
ZBbus Cycle Count and Compare.........................................................................................................58
Timer Registers ....................................................................................................................................59
System Performance Counters .................................................................................................................61
Bus Watcher................................................................................................................................................64
Address Trapping .......................................................................................................................................67
Trace Unit ....................................................................................................................................................70
Trigger Events .......................................................................................................................................70
Trigger Sequences ................................................................................................................................73
Using the Trace Buffer...........................................................................................................................76
Reading the Trace Buffer ......................................................................................................................79
Magic Decoder Ring For Using The Trace Buffer .................................................................................81
Connections to the Trace Logic.............................................................................................................83
Trace Example 1: All CPU0 Activity ......................................................................................................84
Trace Example 2: Network Packet Headers..........................................................................................85
Section 5: L2 Cache .......................................................................................................... 89
Introduction.................................................................................................................................................89
Normal Operation .......................................................................................................................................89
Using the L2 Cache as Memory.................................................................................................................91
Standard RAM .......................................................................................................................................92
Memory Locked in the L2 Cache...........................................................................................................92
Comments on Using the L2 as Memory ................................................................................................93
Reduced Cache Size.............................................................................................................................94
Cache Management Access ......................................................................................................................94
Standard Management Mode Accesses (both ECC_diag address bits zero) .......................................97
ECC Diagnostic Management Accesses (ECC_diag bits nonzero) ......................................................98
Page vi
B roa dcom Co rpo rat ion
User Manual
10/21/02
Document 1250_1125-UM100CB-R