Ecc; Sdram Timing - Broadcom BCM1250 User Manual

User Manual
10/21/02
• Initialization of the DRAMs must be done before the large_memory bit is set. It must be done for each of
the real chip selects by stepping through the eight patterns of the chip select field in the mc_drammode
register. (Note that setting a bit in the chip select field will assert the active low external signal, so to cover
all eight external chip selects {cs3,cs2} should count through the four values with {cs1,cs0} set to both
2'b01 and 2'b10.)
• If the large memory mode is used with parts that use fourteen row address bits (i.e. that need A13) then
the ram_with_A13 bit must be set in the mc_drammode register, this causes bits [15:14] from the row
address mask to be passed to CS[3:2] rather than bits [14:13].
• The page policy should be set to always close page or cas-time-check. Memory accesses will have
UNPREDICTABLE results if other page policies are used.
• The refresh rate should be set in the usual way based on the requirement of the SDRAM parts used. The
controller will issue refresh to two (of the eight) chip selects at a time (rather than one of four).

ECC

The memory controller supports an 8 bit ECC calculated over the 64 bit data. Single bit errors will be detected
and automatically corrected as the data passes through the controller. Double bit errors are detected. In either
case the data is flagged appropriately when it is sent on ZBbus, correctable errors are counted by the SCD;
uncorrectable errors will be counted and report a data error at their destination.
Single bit ECC errors will be corrected during the read and the corrected data will be written back into the
memory. They will continue to occupy the RQQ entry until the data has been written. Thus a memory location
should not return multiple single bit ECC errors. Double bit errors are left as such, so repeated reads of the
data will continue to give the error.
ECC checking can be disabled either to support non-ECC DIMMs or during memory testing.
The memory controller can be set to write bad ECC to the memory in order to check the error handling logic
and code. There are two registers mc_test_data which is 64 bits and mc_test_ecc which is 8 bits. If either of
these are non-zero then during memory writes any bits that are set in these two registers will cause the
corresponding data or ECC bit to be inverted during a memory write. This will force an error into the memory.
If the location is subsequently read an ECC error should be reported.
SDRAM T
IMING
The timing for DDR SDRAM accesses is set per channel, so all parts on a single channel have common timing.
The memory pipeline control queue and scheduler is driven from the timing information programmed for the
channel and will compute its schedule to match the rules. The base timing is set by the memory clock
programmed in the mc_clock_cfg register, this is divided down from the ZBbus clock as outlined in
Section: "Clock Ratios and Clocking Scheme" on page
The mc_timing1 and mc_timing2 registers are used to configure the number of memory clock cycles required
between critical events. These can be obtained from the data sheet for the SDRAM that is being used (or the
common JEDEC timing specification for standard parts). Most of the fields in these registers are four bits so
can be set to a value between 0 and 15, however the acceptable range for the parameters is smaller than this
in many cases. Programming the fields outside their acceptable ranges has UNDEFINED results.
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Section 6: DRAM Page 125