BCM1250/BCM1125/BCM1125H
The complex trap can also use the cacheability attributes to determine if the request matches the trap. The
trap can be set to trigger if the access is Uncached, Cacheable Coherent or Cacheable Non-coherent. It can
also only trigger for requests that do not match the expected cacheability. This can aid debugging by detecting
accesses to areas of the address space that are made with the wrong attribute. The complex traps use the
occurrence counter in the same way as simple traps.
When an access hits the trap (ignoring the value of the occurrence counter) a signal is provided to the trace
trigger logic (described in
(Section: "System Performance Counters" on page
Bits
Name
3:0
addr_trap_index
7:4
reserved
Bits
Name
63:0
value
Bits
Name
4:0
addr_trap
39:5
addr_trap
63:40
reserved
Bits
Name
39:0
addr_trap_up
63:40
reserved
Page
68
Section 4: System Control and Debug Unit
Section: "Trigger Events" on page
Table 40: Address Trap Trigger Index Register
addr_trap_index - 00_1002_00B0
READ ONLY
Default
4'b0
Trap that triggered the interrupt.
4'h0
Reserved
Table 41: Address Trap Trigger Debug Register
addr_trap_reg_debug - 00_1002_0460
READ ONLY
Default
64'hx
This register contains the same information as the addr_trap_reg register, but
reads do not have any side effects.
Table 42: Address Trap Trigger Address Register
addr_trap_reg - 00_1002_00B8
READ ONLY, Read clears interrupt
Default
5'h0
Always reads as zero.
35'h0
Address that triggered the interrupt.
24'h0
Reserved
Table 43: Address Trap Range Top Address Registers
addr_trap_up_0 - 00_1002_0400
addr_trap_up_1 - 00_1002_0408
addr_trap_up_2 - 00_1002_0410
addr_trap_up_3 - 00_1002_0418
Default
40'hx
Top address in range to compare.
24'h0
Reserved
B r oadco m C orp or ati on
70) and to the performance counter selector
61).
Description
Description
Description
Description
Document
User Manual
10/21/02
1250_1125-UM100CB-R
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