The Bcm1250; Figure 1: Bcm1250 Block Diagram - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
T BCM1250
HE
The core of the BCM1250 is an on-chip multiprocessor (CMP) system consisting of two Broadcom SB-1 high
performance MIPS64 CPUs, a shared 512K L2 cache and a DDR SDRAM memory controller. Three integrated
10/100/1000 Ethernet MACs enable easy interfacing to LANs. The three network interfaces can also be
operated together to give two 16 bit wide interfaces that can run full-duplex at OC-48 rates. Two serial ports
are provided for use as UARTs or for WAN connections at up to T3/OC-1 rates (55Mbit/s). High speed I/O is
provided using the HyperTransport (formerly called "Lightning Data Transport" or "LDT") I/O fabric and a 66
MHz PCI (rev 2.2) local bus. To enable low chip count systems the BCM1250 includes a configurable generic
bus that allows glueless connection of a boot ROM or flash memory and simple I/O peripherals. On-chip debug,
trace and performance monitoring functions assist both hardware and software designers in debugging and
tuning the system. The system can be run either big endian or little endian.
Page 2 Section 1: Introduction

Figure 1: BCM1250 Block Diagram

B r oadco m C orp or ati on
User Manual
10/21/02
19.2
Document 1250_1125-UM100CB-R