User Manual
10/21/02
TXC/RXC[2] is used to indicate the validity of the upper 8-bits of data. It should be the same as TXC/RXC[0]
except for the final data in a packet that has an odd number of bytes.
Data Not Valid
Start of Packet, 2 Bytes Valid
Middle of Packet, 2 Bytes Valid
End of Packet, 1 Byte Valid
End of Packet, 2 Bytes Valid
Error
16-B
E
IT
NCODED
The 16-bit encoded Packet FIFO mode is shown in
data they accompany. The encoding is chosen to allow easy conversion to and from POS-PHY Level 3
signalling, which is a wider slower packet bus. The flow control signal runs in the opposite direction to the data.
Figure 65
shows two packets being sent. In the first the sender is unable to supply data for one cycle and
removed the valid signal. In the second packet the receiver asserts the flow control signal for a cycle requesting
a pause from the sender. The transmitter will see the flow control request on the next rising edge of the clock
and will send data for 2-4 cycles before suspending transmission one cycle later. The interface will assert its
flow control output when receive channel flow control is invoked either by one of the DMA channels having
fewer descriptors than the low watermark or by an explicit processor request.
TXC/RXC[2:0]
TXD/RXD[7:0]
TXD/RXD[15:8]
TCLKO/RCLK
TXFC/RXFC
Data Not Valid
Reserved
End of Packet, 1 Byte Valid
End of Packet With Error
Reserved
Document
1250_1125-UM100CB-R
Table 174: Codes for 16-Bit GMII Style Packet FIFO
P
FIFO
ACKET
000
101
111 000
111
100 111
SOP
Figure 65: 16-Bit Encoded Packet FIFO
Table 175: Codes for 16-Bit Encoded Bypass Mode
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
TXC/RXC[2:0]
000
000->101 at start of cycle
101
001->000 at end of cycle
101->000 at end of cycle
111, bit [1] held set until 000
Figure
65. The TXC[2:0] signals indicate the status of the
111
010
000
101 111
EOP
55
SOP
55
TXC/RXC[2:0]
000
001
010
011
100
Section 9: Ethernet MACs Page
111
000
111
110
EOP
FC
299
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