Packet Fifo Interfaces; Table 168: Bcm1125 Ethernet/Fifo Pin Usage - Broadcom BCM1250 User Manual

User Manual
10/21/02
P FIFO I
ACKET
In addition to the standard Ethernet mode, the network interfaces can be put into Packet FIFO mode. In this
mode the Ethernet protocol processing is disabled and the pins are used to provide a simple interface with
either an 8-bit or 16-bit data path each way. The Packet FIFO interface can be clocked at up to 208 MHz or
higher (subject to part speed grade, for full details refer to the hardware data sheet). As can be seen in
Figure 51 on page 265
network interface logic is common to the Ethernet and Packet FIFO modes. The same DMA controller is used
to move data between the packet interface and memory.
There are several modes of Packet FIFO operation, these select the data width and method of framing packets.
The minimum packet size supported in the Packet Fifo modes is 10 bytes, using smaller packets than this will
have UNPREDICTABLE results. The maximum packet size that will be correctly reported is 16K - 1 bytes
(because of the field width in the DMA descriptor) however the interface does not impose a maximum and will
continue receiving as long as there are DMA descriptors available.
The 8-bit Packet FIFO modes simply replace the Ethernet MAC with the simpler Packet FIFO logic. The data
pins remain the same and the data valid (RXDV, TXEN) and error (RXER, TXER) pins are used to signal
framing information. In addition in the encoded mode the collision (COL) and management data (MDIO) pins
get used to provide flow control on the link. Switching between Ethernet and any 8-bit Packet mode only affects
the interface being switched, so there can be any mix of Ethernet and 8-bit Packet interfaces.
The 16-bit Packet FIFO modes do a larger re-configuration of the pins. The Data Sheet gives the mapping from
the Ethernet use to the 16-bit mode uses of the pins. Interface 1 does not support 16-bit modes, the system
behavior will be UNDEFINED if it is configured for 16-bit operation. The reuse of pins causes some restrictions
on the configurations that can be supported when 16-bit Packet FIFO mode is used. If Interface 0 is put in 16-
bit Packet FIFO mode then interface 1 may not be used. If Interface 2 is put in 16-bit Packet FIFO mode then
interface 1 may not be used, and interface 0 can only be used in a Packet FIFO mode.
On the BCM1125/H the interfaces may be configured as two 8-bit interfaces or a single 16 bit interface.
All Interfaces Ethernet or 8-bit Fifo
One 16-bit Packet Fifo
The valid combinations for a BCM1250 are:
• Interface 0 in 16-bit Packet mode, Interface 1 disabled, Interface 2 in Ethernet mode.
• Interface 0 in 16-bit Packet mode, Interface 1 disabled, Interface 2 in 8-bit Packet mode.
• Interface 0 in 16-bit Packet mode, Interface 1 disabled, Interface 2 in 16-bit Packet mode.
• Interface 0 in 8-bit Packet mode, Interface 1 disabled, Interface 2 in 16-bit Packet mode.
Document 1250_1125-UM100CB-R
NTERFACES
the Packet FIFO engine sits to the side of the Ethernet MAC unit, but most of the

Table 168: BCM1125 Ethernet/Fifo Pin Usage

B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
E0_ pins
GMII or 8 bit Fifo E0_
16-bit Packet Fifo F_
E1_ pins
GMII or 8-bit Fifo E1_
Section 9: Ethernet MACs Page 291