Table 79: Chip Select Start Address Register; Table 80: Chip Select End Address Register - Broadcom BCM1250 User Manual

User Manual
10/21/02
Bits Name Range
60 w2rIdle 0-1
61 r2wIdle 0-1
62 r2rIdle 0-1
63 reserved 0
Bits Name
63:0 reserved Reserved
Default
Bits Name
15:0 cs0_start 16'h0000
31:16 cs1_start 16'h0010
47:32 cs2_start 16'h0020
63:48 cs3_start 16'h0030
Default
Bits Name
15:0 cs0_end 16'h0010
31:16 cs1_end 16'h0020
47:32 cs2_end 16'h0030
63:48 cs3_end 16'h0040
Document 1250_1125-UM100CB-R
Table 77: SDRAM Timing Register
mc_timing1_0 - 00_1005_1160
mc_timing1_1 - 00_1005_2160
Default
1'b1 Number of idle cycles required for write to read turnaround.
This bit must always be set.
1'b1 Number of idle cycles required for read to write turnaround.
If this bit is 0 one idle cycle is used.
If this bit is 1 two idle cycles are used.
Usually set for half cycle CAS latencies and cleared otherwise.
1'b1 Number of idle cycles required for read to read of a different chip turnaround.
If this bit is 0 one idle cycle is used.
If this bit is 1 two idle cycles are used.
This bit is usually 0.
1'b0 Reserved
Table 78: SDRAM Timing Register 2
mc_timing2_0 - 00_1005_1180
mc_timing2_1 - 00_1005_2180

Table 79: Chip Select Start Address Register

mc_cs_start_0 - 00_1005_11A0
mc_cs_start_1 - 00_1005_21A0
Default
Ch0 Ch1 (BCM1125/H)
16'h0100 16'h0000
16'h0000 16'h0010
16'h0000 16'h0020
16'h0000 16'h0030

Table 80: Chip Select End Address Register

mc_cs_end_0 - 00_1005_11C0
mc_cs_end_1 - 00_1005_21C0
Default
Ch0 Ch1 (BCM1125/H)
16'h0200 16'h0010
16'h0000 16'h0020
16'h0000 16'h0030
16'h0000 16'h0040
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
(Cont.)
Description
Description
Default
Ch1
Chip select 0,1,2,3 region start address bits [39:24].
These address are in the memory address space (after
the translation described in
Section: "Mapping" on page
Default
Ch1
Chip Select 0,1,2,3 region end address + 1 bits [39:24].
These address are in the memory address space (after
the translation described in
Section: "Mapping" on page
Description
109).
Description
109).
Section 6: DRAM Page 141