Figure 31: Sending The Whole Packet In Asic Mode - Broadcom BCM1250 User Manual

User Manual
10/21/02
Figure 31 shows a full packet being sent using ASIC mode. In this case the asicxfr_size is set to its maximum
value (which is greater than the maximum packet size) ensuring the complete packet is sent to the ASIC.
The first cache block is sent to the SOP address, formed by adding the channel number bits and the 01 SOP
code bits to the base address. This line includes the prepended first doubleword of the DMA descriptor (dscr_a)
in the lowest 8 bytes. Subsequent blocks are sent to the MOP address until the last block. The final block is
sent to the EOP address formed by adding the channel number bits, the 10 EOP code and the number of valid
bytes to the base address. The valid byte count is needed because a full 32 byte block is always sent. Once
the complete packet has been sent the DMA controller will write the length and status flags back into the
descriptor in the normal way. The next descriptor will be fetched for the next packet (so the B buffer is never
used). The ASIC can process the packet, and write data back to memory at the address given in the prepended
dscr_a.
The ASIC needs a way to inform the CPU that its processing is complete. The DMA controller will generate the
end of packet (or completion or watermark) interrupt when it has sent the full packet to the ASIC and has written
the status back into the descriptor. There is a latency in the buffering between the interface and the ASIC, the
ASIC will take time to process the packet and there will be latency writing the result back to memory, so any
interrupts from the DMA controller are likely to be seen by the CPU before the ASIC has completed processing
the packet. A simple way for the ASIC to do this is to send a HyperTransport interrupt message after writing
the last data. The HyperTransport protocol, and host bridge will ensure that the ordering is maintained and the
CPU does not receive the interrupt until the data of the write is visible in the coherency protocol.
Document 1250_1125-UM100CB-R
D
S
C
R
A
8
32 32
SOP MOP
Sent to
Base +
256k * Ch +
Base + 256k* Ch + 64k * 0
64k *1
asic_xfr_en=1
pre_addr_en=1
asic_xfr_size=MAX (lFF)

Figure 31: Sending the Whole Packet in ASIC Mode

B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
32 32
32
MOP MOP MOP
Sent to
valid
32
EOP
Base +
256k * Ch +
64k * 2 +
2048 * valid
Section 7: DMA Page 161