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USER MANUAL

BCM1250/BCM1125/BCM1125H

User Manual for the BCM1250, BCM1125, and

BCM1125H

1250_1125-UM100CB-R

16215 Alton Parkway

•

P.O. Box 57013

•

Irvine, CA 92619-7013

• Phone:

949-450-8700

• Fax:

949-450-8710

10/21/02

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Page 1 USER MANUAL BCM1250/BCM1125/BCM1125H User Manual for the BCM1250, BCM1125, and BCM1125H 1250_1125-UM100CB-R 16215 Alton Parkway • P.O. Box 57013 • Irvine, CA 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710 10/21/02...
Page 2 EVISION ISTORY Revision Date Change Description 1250-UM100-R 06/25/01 Initial release. 1250-UM101-R 01/02/02 New Sections: Section : “Interrupts” on page 47 Section : “ZBbus Cycle Count and Compare” on page Section : “Reduced Cache Size” on page Section : “Cache Configuration Register” on page Section : “DDR FCRAMs”...
Page 3 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Revision Date Change Description 1250_1125- 10/21/02 This list summarizes the major changes between 1250-UM101 and 1250_1125- UM100CB-R UM100. The 1250_1125-UM100CB version of this manual has change bars indicating all changes between the older and newer versions.
Page 4 All rights reserved Printed in the U.S.A. ® ® Broadcom and the pulse logo are trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners.
Page 5: Table Of Contents
CPU Speculative Execution ........................16 Error Conditions............................17 Cache Error Exceptions ........................17 Bus Error Exceptions ..........................18 CPU to CPU Communication (BCM1250 Only) ..................19 External Interrupts ............................. 19 Overview of the ZBbus Protocol....................... 20 Arbitration.............................. 21 Address Phase............................22 Response Phase...........................
Page 6 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 System Control ............................41 Mailbox Registers ............................46 Interrupts ..............................47 HyperTransport Interrupts ........................48 The Full Interrupt Mapper ........................50 Timers ................................57 Watchdog Timers ..........................57 General Timers............................58 Timer Special Cases ..........................58 ZBbus Cycle Count and Compare......................58 Timer Registers ............................59 System Performance Counters .........................61 Bus Watcher..............................64...
Page 7 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Cache Configuration Register ....................... 99 Example Startup Code to clear the L2 Cache..................99 Registers ..............................100 Section 6: DRAM ......................103 Introduction .............................. 103 A Comment on the term Bank......................103 Memory Controller Architecture ......................104 Memory Access Sequencing ......................
Page 8 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Unaligned Buffer Descriptor format for Ethernet DMA ................154 DMA Coherence and Cache Options ......................155 DMA Configurations ..........................156 Ethernet and Serial DMA Engines......................157 Descriptor Count Watermarks ......................157 Completion Interrupts ..........................158 Explicit Descriptor Interrupts........................158 ASIC Mode Transfers ..........................159 Option and Flag Bits for Ethernet MACs ....................171...
Page 9 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Big Endian System: Match Byte Lanes ....................202 Big Endian System: Match Bit Lanes ....................203 Viewing Endian Policy as an Optimization ..................204 Accessing the SiByte from PCI Devices ....................205 Accessing the SiByte from HyperTransport Devices ................210 Force Isochronous Mode Address Range ...................
Page 10 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Buffer Control: TxBufCountMax and DataBufAlloc...............260 HyperTransport Resets ........................260 Section 9: Ethernet MACs ....................264 Introduction...............................264 Interface Overview............................265 Protocol Engine and GMII/MII ........................267 Ethernet Frame Format ........................268 Prepended Header Frame Format ......................270 Protocol Engine Configuration......................271 Interface to PHY ..........................271 Transmitter Operation ..........................272...
Page 11 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 8-Bit EOP Flagged Packet FIFO ......................298 16-Bit Packet FIFO Operation ......................... 299 16-Bit GMII Style Packet FIFO......................299 16-Bit Encoded Packet FIFO ......................300 Restrictions When Resetting the Interface .................... 301 MAC Registers............................302 Section 10: Serial Interfaces ................... 321 Introduction ..............................
Page 12 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Line Interface Configuration ........................352 Synchronous Serial Interrupts ........................352 Synchronous Serial Loopback ........................352 RMON Counters ............................353 Synchronous Serial Register Summary ....................354 Section 11: Generic/Boot Bus..................362 Introduction...............................362 Overview..............................362 Configuring a Chip Select Region......................363 Address Range............................363 Cacheable Access Blocking ........................364 Generic Bus Parity..........................364...
Page 13 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Section 13: GPIO......................397 Introduction .............................. 397 The GPIO Pins ............................397 GPIO Registers ............................399 Other Pins That Can Be Used ......................... 401 Serial Ports ............................401 PCI ..............................401 MACs ..............................401 PCMCIA Power Control Pins ......................401 Section 14: Serial Configuration Interface ..............
Page 14 Data Register............................439 EJTAG Control Register ........................440 Differences from EJTAG 2.5 (Feb. 22, 2000) Specification ..............442 Section 16: Reference..................... 446 Internal Register Addresses by Function....................446 BCM1250/BCM1125/H Internal Registers Ordered by Address............464 B roa dcom Co rpo rat ion Page Document 1250_1125-UM100CB-R...
Page 15 Figure 3: BCM1250 Signals..........................7 Figure 4: BCM1125/H Signals ..........................8 Figure 5: Logical Block Diagram of BCM1250 and BCM1125/H ................ 9 Figure 6: Internal Control and Status Register Alignment ................11 Figure 7: Decision Tree for Memory Space Address Accesses ............... 26 Figure 8: Clock Distribution Overview ......................
Page 16 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Figure 33: Example 1 - TCP checksum a packet....................181 Figure 34: Example 2 - Preparing an iSCSI packet ..................182 Figure 35: Example 3 - Fragmenting an iSCSI packet..................183 Figure 36: PCI and HyperTransport Organization ..................191 Figure 37: Address Ranges for CPU Access to PCI and HyperTransport ............193 Figure 38: Little Endian System ........................201...
Page 17 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Figure 68: Example Reception Using RIN as Active High Enable (sampling on the falling clock edge) ..340 Figure 69: Example Reception Using RIN as Active High Sync (sampling on the falling clock edge) ... 342 Figure 70: Example Transmission Using TIN as Active High Enable (Driving/Sampling on Rising Clock Edge) .
Page 18 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 B roa dcom Co rpo rat ion Page xviii Document 1250_1125-UM100CB-R...
Page 19 Table 8: Static Configuration Options......................27 Table 9: Core and HyperTransport Clock Settings..................31 Table 10: Overview of BCM1250 Physical Address Map ................34 Table 11: Address Map Details ........................36 Table 12: System Identification and Revision Register ................... 42 Table 13: Part Revisions ..........................
Page 20 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 33: System Performance Counter Sources ...................62 Table 34: Bus Watcher Counters ........................64 Table 35: Bus Watcher Error Status Register ....................65 Table 36: Bus Watcher Error Status Debug Register ..................65 Table 37: Bus Watcher Error Data Registers....................65 Table 38: Bus Watcher L2 ECC Counter Register...................66...
Page 21 Table 70: Adjustment Percentages and Multiplier for Values of DLL M ............128 Table 71: First DQS Window Opening and Closing (Typical)................ 132 Table 72: Memory Channel Configuration Register on BCM1250 ..............135 Table 73: Memory Channel Configuration Register on BCM1125/H............. 136 Table 74: Memory Clock Configuration Register ...................
Page 22 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 103: Unaligned Buffer Format DMA Descriptor Second Doubleword ..........170 Table 104: Status Flags for Ethernet Receive Channel .................171 Table 105: Option Flags for Ethernet Receive Channel ................172 Table 106: Status Flags for Ethernet Transmit Channel ................172 Table 107: Option Flags for Ethernet Transmit Channel ................173...
Page 23 Table 167: RMON Counters .......................... 289 Table 168: BCM1125 Ethernet/Fifo Pin Usage ..................... 292 Table 169: BCM1250 Ethernet/Fifo Pin Usage ..................... 293 Table 170: Codes for GMII Packet FIFO Mode ..................... 295 Table 171: Codes for 8-Bit Encoded Bypass Mode..................296 Table 172: Codes for 8-Bit SOP Packet FIFO....................
Page 24 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 173: Codes for 8-Bit EOP Bypass Mode....................298 Table 174: Codes for 16-Bit GMII Style Packet FIFO ..................300 Table 175: Codes for 16-Bit Encoded Bypass Mode ..................300 Table 176: MAC Configuration Registers ......................302 Table 177: MAC Enable Registers.........................306 Table 178: MAC Transmit DMA Control Register ..................306...
Page 25 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 208: DUART Input Port Change Status Register for Channel A ............331 Table 209: DUART Input Port Change Status Register for Channel B ............331 Table 210: DUART Output Port Control Register..................331 Table 211: DUART Per Channel Output Control Registers................332 Table 212: DUART Aux Control Register ......................
Page 26 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 243: Serial Address Mask Register......................359 Table 244: Serial Address Match Register ....................359 Table 245: Sequencer Table Entries ......................359 Table 246: Serial RMON Counters ........................360 Table 247: Byte Lanes for the Generic Bus ....................363 Table 248: Generic Bus Timing Parameters ....................366 Table 249: Burst Cycle Summary ........................372...
Page 27 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 278: GPIO Read Register........................399 Table 279: GPIO Input Invert Control Register....................399 Table 280: GPIO Glitch Filter Select Register ....................400 Table 281: GPIO Direction Register ......................400 Table 282: GPIO Pin Clear Register ......................400 Table 283: GPIO Pin Set Register.........................
Page 28 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 B roa dcom Co rpo rat ion Page xxviii Document 1250_1125-UM100CB-R...
Page 29: Section 1: Introduction
VPN access, firewalls, gateways The different members of the family target different performance points and applications, while retaining software compatibility. This User Manual covers the dual-processor BCM1250, and the uni-processor BCM1125 and BCM1125H parts. All the parts use the SB-1 CPU core. This is a high performance implementation of the standard MIPS64 instruction set architecture.
Page 30: The Bcm1250
HyperTransport (formerly called “Lightning Data Transport” or “LDT”) I/O fabric and a 66 MHz PCI (rev 2.2) local bus. To enable low chip count systems the BCM1250 includes a configurable generic bus that allows glueless connection of a boot ROM or flash memory and simple I/O peripherals. On-chip debug, trace and performance monitoring functions assist both hardware and software designers in debugging and tuning the system.
Page 31: The Bcm1125 And Bcm1125H
BCM1125 BCM1125H The core of the BCM1125 and BCM1125H is a uniprocessor system consisting of a Broadcom SB-1 high performance MIPS64 CPU, a 256K L2 cache and a DDR SDRAM memory controller. Two integrated 10/100/ 1000 Ethernet MACs enable easy interfacing to LANs. The two network interfaces can also be operated together to give a 16 bit wide interface that can run full-duplex at OC-48 rates.
Page 32: Other Documentation
User Manual 10/21/02 THER OCUMENTATION Most of the example designs and Application Notes for the BCM1250 also apply to the BCM1125 and BCM1125H. Documentation useful to users of all the devices includes: • SB-1 Core Processor User Manual (SB-1-UM00-R) •...
Page 33: Terminology
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ERMINOLOGY Numbers used in data fields of this document follow the verilog convention of giving the field size in decimal, followed by a quote (’), a character representing the base (b for binary, d for decimal or h for hexadecimal) and the number.
Page 34 BCM12500 which lack some of the peripheral functionality. Broadcom Use Only registers and operations are intended for use by Broadcom in testing the device. In most cases this manual does not describe these options in sufficient detail for them to be safely used. Incorrect settings of these registers or inappropriate use of operations may cause the system to behave in UNDEFINED ways, or require the system to be power cycled to restore operation.
Page 35: Section 2: Signal Overview
BCM1250 S IGNAL ROUPS The signal pins of the BCM1250 can be divided into functional groups, primarily related to the peripheral to which they are attached. Hardware designers should refer to the BCM1250 Data Sheet for full pinout and timing details.
Page 36: Bcm1125/H Signal Groups
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 BCM1125/H S IGNAL ROUPS The signal pins of the BCM1125 and BCM1125H can be divided into functional groups, primarily related to the peripheral that they are attached to. Hardware designers should refer to the BCM1125/H Data Sheet for full pinout and timing details.
Page 37: Section 3: System Overview
10/21/02 Sec t ion 3 : Sys t em Over view NTRODUCTION A logical block diagram of the BCM1250 and BCM1125/H family is shown in Figure 5. This figure does not exactly match the implementation details, but it gives a more useful model for programmers and system designers to use.
Page 38 The processors are Broadcom SB-1 CPUs implementing the MIPS64 architecture. These are described in detail in the SB-1 User Manual. On the BCM1250 the two CPUs are identical in all respects apart from the processor number that will be read from the Processor Identification register (CP0 register 15). The reset logic in the System Control and Debug unit (SCD) is different for the two processors.
Page 39: Internal Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 NTERNAL EGISTERS There are a large number of internal registers. Their definitions are given in the sections of this manual that describe their use. Section: “Internal Register Addresses by Function” on page 446 has a summary of all the register addresses.
Page 40: Coherence
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 When a register is marked as cleared by a read it will be cleared by any read to it. Care should therefore be taken to ensure that a compiler or debugger does not split an access to the register into multiple reads. For...
Page 41 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Blocks with main memory addresses should be marked coherent in the CPU. If these blocks are not shared there is no difference in performance between marking them cacheable coherent and cacheable non-coherent, but there is a much higher chance of unexpected behavior if the block is marked non-coherent (for example due to false sharing or missing cache flushes before DMA operations).
Page 42: Ordering Rules And Device Drivers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 RDERING ULES AND EVICE RIVERS The interaction between the ordering rules imposed by the SB-1 CPU, the ZBbus and the peripheral agents simplifies device programming in most situations. In these situations it is the ordering between cacheable coherent memory and uncacheable peripheral registers that is important.
Page 43 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Rule (7) is a potential problem, since writes could pass earlier reads to the same device (and thus the read could see the state after the write completes). However, rule (4) ensures that this situation never arises for code running on the SB-1.
Page 44: Cpu Speculative Execution
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 CPU S PECULATIVE XECUTION The SB-1 CPU can speculatively execute cacheable loads (i.e. a read is issued to the ZBbus to get the data before the load is guaranteed to graduate), this only happens if the load is canceled because of an exception on an earlier instruction (branches are always resolved before the load is committed).
Page 45: Error Conditions
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 RROR ONDITIONS The system makes every effort to ensure that processing is never done based on erroneous data. Error conditions are signalled in several ways, as well as being passed in a flag with the data. All the critical structures where data corruption could occur are protected with ECC (allowing for correction of single bit errors) or parity (in structures that never contain the only copy of the data).
Page 46: Bus Error Exceptions
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 RROR XCEPTIONS The bus error exception is raised on the CPU by external errors that are not reporting data corruption. The main cause is when an access is detected to a non-existent address. Cacheable accesses that result in a bus error will be put in the cache with uncorrectable ECC errors (as described for the cache error exception).
Page 47: Cpu To Cpu Communication (Bcm1250 Only)
(BCM1250 O OMMUNICATION The two CPUs in a BCM1250 can communicate and share information in several ways. The MIPS Load Linked (ll and lld) and store conditional (sc and scd) instructions can be used to implement atomic operations. When there is genuine sharing, the L1 cache to L1 cache latency is 28-36 CPU cycles.
Page 48: Overview Of The Zbbus Protocol
Agent Description CPU0 SB-1 CPU 0. CPU1 SB-1 CPU 1. (Only in BCM1250) IOB0 I/O Bridge 0, connects PCI and HyperTransport interfaces to the ZBbus. IOB1 I/O Bridge 1, connects the MACs and slow speed peripheral interfaces to the ZBbus.
Page 49: Arbitration
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 2: ZBbus Signals (Cont.) Data Section D_DA[255:0] Data. There is valid data only on the byte lanes that had byte enables set (on A_BYEN) in the A-phase. The data on the other byte lanes is UNPREDICTABLE.
Page 50: Address Phase
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 DDRESS HASE In the address phase the requesting agent puts the TID, address, byte-enables, command and cache attributes onto the address bus. All agents will examine the request and respond by setting their R_SHD and R_EXC bits in the R-phase.
Page 51: Response Phase
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Two fields describe the cache attributes of a transfer. The first, shown in Table 4, describes the base (Level 1 cache) attribute. This must be set consistently by all agents using a block or all accesses to the block become UNPREDICTABLE.
Page 52: Data Phase
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 HASE The data transfer ends a transaction, and takes place in the Data phase. Since the latency between the A- phase request and the data becoming available can be very long, the D-phase is completely decoupled from the A-phase.
Page 53 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 6: ZBbus Data Status Codes (Cont.) D_CODE[2:0] Status of Data on D_DA Sources of Error Bus error. A CPU will take a bus error exception I/O bridge0: PCI parity error, master or target if it receives this error.
Page 54: Reset
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Read Shared or Exclusive Write or Write & Invalidate (Memory Space Address) (Memory Space Address) Memory Memory Write Read Memory Write L2 Cache L2 Write if Hit Write Error condition -Some Agent is unable Exclusive to determine ownership...
Page 55: Table 7: Operation Of Different Reset Sources
IO_CLK100 will match the internal clocking and will run at a few MHz (typically less than 10MHz) during COLDRES_L. ldt_minrstcnt Broadcom Use Only. Normal Operation. Enable HyperTransport reset test mode. ldt_bypass_pll Broadcom Use Only. Normal Operation. Bypass the HyperTransport PLL.
Page 56 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 8: Static Configuration Options (Cont.) IO_AD Name Pulled Up to 3.3V Pulled Down Section ser0_enable Serial port 0 is synchronous. Serial port 0 is UART A. Section: “Synchrono This sets the reset configuration, software may change it.
Page 57 After a system reset (or power-on reset) CPU 0 and all peripherals are brought out of reset, but on a BCM1250 CPU 1 continues to be held in reset and will be isolated from the system. This allows CPU 0 to perform essential system initialization before releasing CPU 1.
Page 58 // No internal way to tell between an external RESET_L // and a Watchdog timeout else resetType = ResetLOrWatchdog // later BCM1250 have a flag for watchdog reset if BCM1250 stepping C0 or later if watchdog wd_has_reset bit set resetType = Watchdog...
Page 59: Clocks
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The system_scratch register could be used as an alternative to using the configuration bit for the serial port. The software would have to put a unique value into the register (or could set a bit that is reserved for this purpose) before writing the system_reset bit.
Page 60 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 9: Core and HyperTransport Clock Settings (Cont.) Main PLL (Code from Reset HyperTransport PLL (Code from HyperTransport Time IO_AD[11:7]) Frequency Register) CPU Clock ZBbus Clock HyperTransport Clock HyperTransport Data Rate Code Ratio (MHz) (MHz) (MHz)
Page 61: Figure 8: Clock Distribution Overview
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The memory clock is synchronously divided down from the CPU clock. The divide ratio is programmed into the memory controller configuration registers. Figure 8 gives an overview of the internal clock generation. Core Clock to CPU0, CPU1, L2 Cache ÷...
Page 62: Memory Map
PCI and HyperTransport endian policies). An overview of the memory map is given in Table 10 Figure 9 and a more detailed view is in Table 11 on page Table 10: Overview of BCM1250 Physical Address Map Base Owner 00_0000_0000 00_0FFF_FFFF Memory controller.
Page 63: Figure 9: Memory Map
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The memory controller supports up to 1 GB of memory in a system that is restricted to 32-bit physical addresses, and up to 4 GB ( 2 GB on BCM1125/H) using 512 Mb technology DRAMs (up to 8 GB when 1Gb technology SDRAMs are available, and with an option to double the size at the cost of speed with an external decoder) on systems with a full 40-bit address.
Page 64: Table 11: Address Map Details
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 11: Address Map Details Base Size Owner 00_0000_0000 00_0FFF_FFFF 256 MB Base DRAM. 00_1000_0000 00_1001_FFFF 2*64 KB Reserved/Debug JTAG serviced addresses. 00_1002_0000 00_1002_0FFF 4 KB Reset config, CPU 0 interrupt mapper, timers, addr trap, trace, bus log and counters.
Page 65 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 11: Address Map Details (Cont.) Base Size Owner 00_D800_0000 00_D8FF_FFFF 16 MB EOI signaling.Match byte lane endian policy. (Reserved on BCM1125) 00_D900_0000 00_D90F_FFFF 1 MB Iack signaling. Match byte lane endian policy. (Reserved on BCM1125)
Page 66 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 11: Address Map Details (Cont.) Base Size Owner FE_0000_0000 FF_FFFF_FFFF 8 GB Reserved B r oadco m C orp or ati on Page Section 3: System Overview Document 1250_1125-UM100CB-R...
Page 67 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 This Page is left blank for notes B r oadco m C orp or ati on Document 1250_1125-UM100CB-R Section 3: System Overview Page...
Page 68 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 This Page is left blank for notes B r oadco m C orp or ati on Page Section 3: System Overview Document 1250_1125-UM100CB-R...
Page 69: Section 4: System Control And Debug Unit
Many bits of the system_cfg port are only writable from the JTAG port. They provide access to test features and are reserved for use by Broadcom. They must be left at zero for normal operation of the part. B r oadco m C orp or ati on...
Page 70: Table 12: System Identification And Revision Register
10/21/02 The uniprocessor bits and soft-reset bit may be used on the BCM1250 to disable one of the processors. The clock to the disabled processor will be stopped following reset and it will enter a low power state (lower power than being left in reset).
Page 71: Table 14: Manufacturing Information Register
Read Only, reflects the strap resistor on IO_AD[1] that selects the source for the internal 100MHz clock and IO_CLK100 (if enabled). ldt_minrstcnt Read Only, reflects the strap resistor on IO_AD[2]. Broadcom Use Only. This must be zero for normal operation. ldt_bypass_pll Read Only, reflects the strap resistor on IO_AD[3].
Page 72 IO_CLK100. If this bit is zero then the IO_CLK100 will be held in a high impedance state. ldt_test_en Read Only, reflects the strap resistor on IO_AD[24]. Broadcom Use Only. This must be zero for normal operation. gen_parity_en Read Only, reflects the strap resistor on generic IO_AD[25] that configured the generic bus parity.
Page 73: Table 16: Scratch Register
1'b0 When written with a 1 a full system reset will be performed (thus setting this bit back to zero). misr_mode 1’b0 Broadcom Use Only. scd_misr_reset 1’b0 Broadcom Use Only. sw_flag 1’bx This read/write bit is cleared by a cold reset. Its value is preserved on any other reset.
Page 74: Mailbox Registers
Each CPU has a mailbox register that can be used to signal events or small messages. The register may be accessed by the other CPU (on a BCM1250) or a bus master peripheral. If the part is a device on the PCI bus (i.e.
Page 75: Interrupts
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 NTERRUPTS The chip has a large number of interrupt sources. These come from both internal peripherals and external signals. Each CPU has its own interrupt mapper which allows the destination of the interrupt from each source to be set to one of the six architected hardware interrupts, the non-maskable interrupt (NMI) or the Debug Interrupt (DINT).
Page 76: Hypertransport Interrupts
(having only two CPUs, these amount to the same thing on the BCM1250). The mapper supports the 8 bit destination from the HyperTransport Specification rev 1.0 and earlier, and will ignore the additional 24 destination bits added by the HyperTransport Specification rev 1.01.
Page 77: Table 20: Delivery Of Hypertransport Interrupts
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 19: Interrupt Message Format for Writes to interrupt_ldt_set Register Data Bits Description HyperTransport Interrupt Message Type: 000: Fixed 001: Arbitrated (Low Priority) 010: Non-vectored: SMI 011: Non-vectored: NMI 100: Non-vectored: INIT 101: Non-vectored: Startup 110: Non-vectored: External Interrupt 111: Reserved HyperTransport Interrupt Trigger Mode 0=Edge, 1=Level (non-vectored interrupts must be edge).
Page 78: The Full Interrupt Mapper
The PIC will provide an 8-bit source vector in response to an interrupt acknowledge (IACK) cycle. On the BCM1250 and BCM1125H software is responsible for running the IACK cycle by performing a byte read within the reserved IACK range as described in Section: “Legacy...
Page 79: Figure 10: Per-Cpu Interrupt Mapper (Replicated For Each Cpu; X = 0 Or 1)
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The interrupt_trace register is used to select which interrupts to this CPU are sent to the trace unit to be used as part of a trigger condition. The bits in this register provide an accept mask. Any interrupt that has its corresponding bit set in this register will cause the trigger.
Page 80: Table 21: Interrupt Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The main interrupt registers are all 64 bits wide: Table 21: Interrupt Registers Name Description interrupt_diag Setting a bit in this register raises the corresponding interrupt. Software must clear the bit to remove the interrupt. This register is intended for diagnostics only.
Page 81 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 22: Interrupt Sources (Cont.) Number Name Description Method to clear timer_int_3 General timer 3 Interrupts when timer reaches zero, cleared by a write to the timer configuration register. See Section: “General Timers” on page smb_int_0...
Page 82 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 22: Interrupt Sources (Cont.) Number Name Description Method to clear mac_0_int MAC 0 interrupt Raised by an error in the MAC or when any of the four DMA channels need service. Cleared by reading the mac_status_0 register or servicing the DMA interrupt.
Page 83 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 22: Interrupt Sources (Cont.) Number Name Description Method to clear gpio_int_4 GPIO pin 4 interrupt Interrupts when external source raises an interrupt. If level sensitive, the external source must clear the gpio_int_5 GPIO pin 5 interrupt interrupt.
Page 84 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 22: Interrupt Sources (Cont.) Number Name Description Method to clear ldt_nmi HyperTransport signaled This bit is reserved in the system interrupt register, and comes only from the ldt_interrupt register. This bit is set when an NMI interrupt packet directed to this CPU had been received from the HyperTransport bus.
Page 85: Timers
41), reset just one CPU, or (on the BCM1250) reset both CPUs but no peripherals. Care must be taken if this is done, the reset software will need to probe for devices that are hung or in inconsistent states. The behavior should only be changed from the default in high availability systems or in some cases where the two CPUs are running distinct operating systems.
Page 86: General Timers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ENERAL IMERS The part has four general timers. Each has a 23 bit counter and is clocked by a 1 MHz clock derived from the 100 MHz reference clock. This allows a maximum count of 8388608, giving the maximum one-shot timeout of 8.388608 s, and a maximum periodic interrupt every 8.388608 s.
Page 87: Timer Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 IMER EGISTERS Table 23: Watchdog Timer Initial Count Registers watchdog_timer_init_cnt_0 - 00_1002_0050 watchdog_timer_init_cnt_1 - 00_1002_0150 Bits Name Default Description 22:0 watchdog_timer_init_cnt 23'bx Watchdog timer initial count register. Sets the watchdog timeout time in microseconds. This register should only be written when the timer is disabled.
Page 88: Table 26: General Timer Initial Count Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 26: General Timer Initial Count Registers general_timer_init_cnt_0 - 00_1002_0070 general_timer_init_cnt_1 - 00_1002_0078 general_timer_init_cnt_2 - 00_1002_0170 general_timer_init_cnt_3 - 00_1002_0178 Bits Name Default Description 22:0 timer_init_cnt 23'bx Timer initial count register. This sets the maximum value of the...
Page 89: System Performance Counters
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 29: ZBbus Count Register zbbus_cycle_count - 00_1003_0000 READ ONLY Note 00_1003_0008 - 00_1003_FFFF is safe for user space access Bits Name Default Description 63:0 count 64'h0 Count of ZBbus cycles since reset. Writes will be ignored.
Page 90: Table 32: System Performance Counters
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 31: System Performance Counter Configuration Registers (Cont.) perf_cnt_cfg - 00_1002_04C0 Bits Name Default Description 31:24 Counter 3 source 8'b0 Sets the source for counter 3. clear 1'b0 If this bit is set in a write to the register the counters will be reset, the bit self-clears and always reads as zero.
Page 91 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 33: System Performance Counter Sources (Cont.) Value Condition Counted Interrupt request cycles. The counter is incremented every bus cycle the int_trace_trigger_x output of the interrupt mapper is asserted (see Figure 10 on page 51). This records the time taken from the interrupt assertion to software clearing the interrupt condition.
Page 92: Bus Watcher
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ATCHER The Bus Watcher monitors ZBbus data transfers, detecting error reports. Corrected ECC errors from memory and the L2 cache are counted. Uncorrectable ECC errors are counted and logged. The bus watcher will raise an interrupt when it detects an error.
Page 93: Table 35: Bus Watcher Error Status Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 errors do not raise exceptions or cause the DMA engines to stop, so the Bus Watcher interrupt is likely to be the only way they are reported. Table 35: Bus Watcher Error Status Register bus_err_status - 00_1002_0880...
Page 94: Table 38: Bus Watcher L2 Ecc Counter Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 38: Bus Watcher L2 ECC Counter Register bus_l2_errors - 00_1002_08C0 Should only be written with 32-bit or 64-bit write Bits Name Default Description l2_cor_d_ecc 8'b0 Count of correctable L2 cache data errors, saturates at 8'hff, write the register with zero to clear the count.
Page 95: Address Trapping
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 DDRESS RAPPING There are four address traps in the SCD. An interrupt is raised by any access that falls within the address range specified by a trap. Hits to a trap can also be used to trigger the performance counters and trace unit. The address traps are mainly used as a debugging aid, but they can also be used to detect (but not prevent) illegal accesses in the event of a system failure.
Page 96: Table 40: Address Trap Trigger Index Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The complex trap can also use the cacheability attributes to determine if the request matches the trap. The trap can be set to trigger if the access is Uncached, Cacheable Coherent or Cacheable Non-coherent. It can also only trigger for requests that do not match the expected cacheability.
Page 97: Table 44: Address Trap Range Base Address Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 44: Address Trap Range Base Address Registers addr_trap_down_0 - 00_1002_0420 addr_trap_down_1 - 00_1002_0428 addr_trap_down_2 - 00_1002_0430 addr_trap_down_3 - 00_1002_0438 Bits Name Default Description 39:0 addr_trap_down 40'hx Base address in range to compare. 63:40 reserved 24'h0...
Page 98: Trace Unit
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 RACE The trace unit allows ZBbus activity to be non-intrusively traced. There is a 12KB buffer into which a trace of the address or data activity on the bus can be written. The trace may be read out either by a CPU or through the JTAG interface.
Page 99 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The event is triggered by the data phase if the data_id_match bit is set and the top four bits of the transaction ID on the data bus (which identify the agent that initiated the transfer) match the data_id field, or the resp_id_match bit is set and the responder ID (which provided the data) matches the resp_id field.
Page 100: Table 46: Trace Event Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Each trigger event has a counter associated with it. If the counter is greater than zero when the trigger condition is true then the counter decrements. If the counter is zero then the event is signaled to the trigger sequencers, and the counter will be reloaded with its initial value.
Page 101: Trigger Sequences
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 RIGGER EQUENCES A trigger sequence is a set of up to four conditions that must be satisfied in sequence and a trace function that will be executed when the sequence is complete. The conditions are combinations of trigger events. There are eight trigger sequencers.
Page 102: Table 47: Trace Sequence Control Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 A Sample causes an address/control bundle to be recorded in the trace buffer. These samples are packed three per line of the trace memory, so a maximum of 768 samples can be in the buffer. Note that if the final...
Page 103 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 47: Trace Sequence Control Registers (Cont.) trace_sequence_0 - 00_1002_0A40 trace_sequence_1 - 00_1002_0A48 trace_sequence_2 - 00_1002_0A50 trace_sequence_3 - 00_1002_0A58 trace_sequence_4 - 00_1002_0A80 trace_sequence_5 - 00_1002_0A88 trace_sequence_6 - 00_1002_0A90 trace_sequence_7 - 00_1002_0A98 Bits Field Default Description 17:16 Function 2‘b0...
Page 104: Using The Trace Buffer
JTAG debug interface. Then the system is run and the trace is recorded in the buffer. When the buffer freezes the trace can be read out, again either by software on the BCM1250 or BCM1125/H or via the JTAG link.
Page 105: Table 49: Trace Buffer Address/Control Bundle
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 48: Trace Control Register (Cont.) trace_cfg - 00_1002_0A00 Bits Field Default Description 17:10 trcAddr 8‘b0 Current trace buffer address. If the trcFull bit is not set this number plus 1 entries can be read from the buffer.
Page 106 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 49: Trace Buffer Address/Control Bundle (Cont.) Bits Field Description 63:60 A_DW Encoded byte enables. Indicates any doublewords with valid bytes. DW[n=3:0] = A_BE[8*n + 0] | A_BE[8*n + 1] | A_BE[8*n + 2] | A_BE[8*n + 3] |...
Page 107: Reading The Trace Buffer
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 EADING THE RACE UFFER Each entry in the trace buffer is 384 bits, and falls in to one of two possible formats. Format 1 is used when the entry contains one to three address/control samples, the first bundle (t0) will always come from an address trigger (the ATRIG bit will be 1) and will indicate format 1 by not having an associated data sample (the DTRIG bit will be 0).
Page 108 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 An algorithm for decoding the bundle is: if (b[127]==1) if (b[126]==1) /* Have valid address and valid data sample */ Format = 2 else Format = 1 if (b[255] == 0) /* Have 1 valid address sample */...
Page 109: Magic Decoder Ring For Using The Trace Buffer
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 AGIC ECODER SING RACE UFFER This section includes some notes for using the Trace Buffer when debugging. Nothing in this section is part of the official specification of the device and things (in particular the TID information) could change from revision to revision.
Page 110: Table 52: Encoded Byte Enables For Cpu Transactions
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 52: Encoded Byte Enables for CPU Transactions DoubleWord CPU Operation A_DW Byte A_BYT Comments Cacheable operations always move a full block, so the byte Cacheable fill or 1111 11111111 enables can be ignored. evict or...
Page 111: Figure 11: Connections To Trace Logic
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ONNECTIONS TO THE RACE OGIC The trace logic connects to many other parts of the SCD. Figure 11 shows these connections. ZBbus System Events JTAG Performance Address Match Counters Traps Trace Overflow Interrupt Match Interrupt CPU Interrupts...
Page 112: Trace Example 1: All Cpu0 Activity
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 1: A CPU0 A RACE XAMPLE CTIVITY The code running on CPU0 is being monitored, for a particular section of code all address bus activity will be recorded to check the L2 cache behavior. The code is patched to do a dummy access to an address at the start and end points of the code to trace, and...
Page 113 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 2: N RACE XAMPLE ETWORK ACKET EADERS This example uses the trace buffer as a non-obtrusive record of the most recent network packet headers that were received from one of the MACs. It could be used, for example, when there is a bug that is thought to be caused by the processing of some rare sequence of network packets.
Page 114 Device drivers for PCI devices quite often rely heavily on macros and library input/output routines. Particularly when porting code from a little endian (e.g. x86) driver to the BCM1250 or BCM1125/H running big endian, it can be hard for the programmer to track down exactly what is being transferred back and forth to the device on the PCI bus.
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Page 117: Section 5: L2 Cache
S ec t io n 5 : L 2 Cac he NTRODUCTION The on-chip second level cache is shared by the processors and any I/O DMA masters. On the BCM1250 the L2 cache is 512 KBytes, on the BCM1125/H it is 256 KBytes. This section describes the normal operation of the L2 cache, a mode where banks of it can be used as an on-chip SRAM and the management interface to it.
Page 118 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Every bus request is accompanied by an L2 cacheability flag, if this is set and the block is not in the L2 cache then it will be allocated. On a write miss the L2 will allocate space for the block and accept the data when it is transmitted.
Page 119: Using The L2 Cache As Memory
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 L2 C SING THE ACHE AS EMORY Some applications require more control over the on-chip memory than is provided by a cache, and would work best with a local RAM. A fast RAM can be provided by removing ways from the L2 cache. Each way that is removed from the cache provides a 128 KByte memory that can be accessed at the same speed as the L2 (or 64KB memory on a 256KB cache).
Page 120: Standard Ram
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 TANDARD Ways removed from the L2 cache can be used as a standard RAM block by accessing the memory using the management access address range with the way bits set appropriately and the special control bits set to zero (the management mode is described in Section: “Cache Management Access”...
Page 121: Comments On Using The L2 As Memory
L1 need not be related) which mitigates the effects some amount. But with a smaller L2 there is very likely to be reduced performance. On the other hand on a BCM1250 a 256KB 2 way associative cache (i.e.
Page 122: Reduced Cache Size
EDUCED ACHE The BCM1250 can be used to develop code for lower end members of the SiByte processor family. To allow performance tuning, the L2 cache size can be reduced to match the other parts, otherwise any performance numbers may be skewed by the large L2.
Page 123: Figure 13: Cache Management Address
Index. The cache is divided in to sets, each containing four 32 byte lines. These bits select which set is indexed. The BCM1250 has all 4096 sets, the BCM1125/H has only 2048 so bit 16 is not part of the index.
Page 124 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Management accesses may be done with cacheable or non-cacheable operations. However, the L2 cache will always operate on a full 32 byte cache line. On reads there is not a problem since the destination will filter the data (data is always carried on its natural byte lane on the ZBbus), but writes that are smaller than a cache block will cause random values to be written to the other bytes in the line.
Page 125: Standard Management Mode Accesses (Both Ecc_Diag Address Bits Zero)
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ECC_ TANDARD ANAGEMENT CCESSES BOTH DIAG ADDRESS BITS ZERO Standard management mode accesses are any made to the management address range with the ECC_diag address bits clear. Management reads will return the line from the addressed index and way. The normal ECC checking and correction is performed.
Page 126: Ecc Diagnostic Management Accesses (Ecc_Diag Bits Nonzero)
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ECC D (ECC_ IAGNOSTIC ANAGEMENT CCESSES DIAG BITS NONZERO Management accesses with the ECC_diag field nonzero modify the behavior of the cache to allow access to the raw memory bits for testing. Management reads with the ECC_diag [0] bit set will return the raw data from the addressed index and way.
Page 127: Cache Configuration Register
ODE TO CLEAR THE ACHE The following code will work on the BCM1250 and BCM1125/H using 4096 sets. It could be optimized for the BCM1125/H to only clear 2048 sets. # Save the old status register, and set the KX bit.
Page 128: Registers
READ ONLY Bits Sytem Revision PERIPH_REV3 and later only Cache quadrant information [t,b,r,l] (Broadcom Use Only) l2_cache_disable register value Reads back enable for use of low priority memory blocker from value written as bit [10] in the l2_misc_config register address...
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Page 131: Section 6: Dram
64 bit data path with 8 bit ECC. Each channel can directly support up to two standard two physical bank JEDEC 184 pin DDR DIMMs (for a total of four DIMMs on a BCM1250) running at 133MHz clock (266MHz data rate, sometimes called PC2100 DIMMs based on PC266A parts) and allows for performance to increase as the DIMMs support higher data rates.
Page 132: Memory Controller Architecture
The memory controller consists of a ZBbus interface and one or two memory channel interfaces. The channels on the BCM1250 are numbered 0 and 1, the BCM1125/H only has channel 1. The block diagram is shown in Figure 14 on page 105.
Page 133: Figure 14: Memory Controller Block Diagram
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ZBbus address/cmd write-data read-data Data Buffer Request Queue BCM1250 Only M-channel1 M-channel0 Control Control Addr/cmd M-channel0 M-channel1 Figure 14: Memory Controller Block Diagram Entries are selected for issue from the RQQ based on the state of the other entries and the status returned by the memory pipeline controller for each of the channels.
Page 134 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 When a channel switches from writes to reads (and back) there is a delay while the data bus lines and timing strobes (DQSs) turnaround from the controller driving to the memory driving (or the reverse). To get the best bandwidth from the channel the controller batches writes and reads to minimize the number of these turnaround delays.
Page 135: Memory Access Sequencing
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 EMORY CCESS EQUENCING Certain applications need more control over the memory access pattern than is available using the normal operations in the memory controller, for example when the memory is being used for transaction logging. The controller was designed to optimize the normal case, but there are several methods that software can use to force the sequence.
Page 136: Table 59: Percent Deltas From Popular Dimm Frequencies
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 58: Clock Speed (Cont.) ZBbus Memory Memory Memory Memory Memory Memory CPU Clock Clock Clock 4.5:1 Clock 4:1 Clock 3.5:1 Clock 3:1 Clock 2.5:1 Clock 2:1 66.7 75.0 85.7 100.0 120.0 150.0 61.1 68.8 78.6 91.7...
Page 137: Memory Configurations
HANNEL ELECT On the BCM1250 the two channels may be interleaved or they may be independent. If they are interleaved then they must match in all parameters. When they are interleaved a single address bit is used to select between them. When the channels are independent the start and end address set for the chip select generation will also select between the two channels.
Page 138: Chip Select
A memory controller channel has four active low Chip Selects:CS[3:0]. The address range that they become active for is configurable. On the BCM1250 if the two channels are interleaved then the chip selects for each channel are programmed to an identical address range, which is twice the size of the memory attached to one of the channels.
Page 139 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The address range covered by each of the chip selects is set in the mc_cs_start and mc_cs_end registers. The start address register holds address bits [39:24] that when extended with zeros in bits [23:0] give the lowest address in the range.
Page 140: Example Channel And Chip Select Configurations
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 XAMPLE HANNEL AND ELECT ONFIGURATIONS Configuring the memory map for channels and chip selects is usually straightforward, but there are a few special cases. In this section some example configurations are presented. The values that are set for chip select start and end addresses are shown in the figures, these represent bits [39:24] of the address.
Page 141: Figure 17: Example 1Gb With Two Chip Selects On One Channel
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Figure 17 shows the first configuration. This configuration has chip select 0 for the low half and chip select 1 for the upper half and the start and end addresses of their range are set to reflect this.
Page 142: Figure 18: Example 1Gb With Two Chip Selects Interleaved On One Channel
Figure 18: Example 1GB with two chip selects interleaved on one channel On the BCM1250 there is a higher performance possibility. Rather than putting both physical banks on the same channel one can be put on each channel. This doubles the number of data bits in use (since the controller can run both channels in parallel), allowing twice the peak bandwidth.
Page 143: Figure 19: Example 1Gb With Two Chip Selects Interleaved Across Both Channels
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Figure 19 shows this, with the interleave on a relatively low address bit. Notice that again the chip select ranges are the same for both selects, but in this case they are for different channels. FF_FFFF_FFFF...
Page 144: Figure 20: Example 2Gb With Two Chip Selects Interleaved On One Channel
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Figure 20 it can be seen that 3GB of the aliases are hidden in the memory address space that cannot be accessed from the physical space. The only alias that needs to be considered is the 01_0000_0000 - 01_3FFF_FFFF alias of 00_0000_0000 - 00_3FFF_FFFF.
Page 145: Table 61: Address Bits Used By A Memory Channel
SDRAM address. Each of the memory channels can theoretically address 4GB of memory (for a total of 8GB attached on a BCM1250). This comes from the number of RAS (13 or 14), CAS (12 or 11), bank (2), chip select (2) and bytes in dword(3) = 32 address bits per channel.
Page 146: Table 62: Example For 128 Mbyte Cs Region With 4K Rows, 1K Columns
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Section: “Larger Memory Systems” on page 124 describes a mode of the memory controller that allows external generation of eight chip selects rather than four. This mode does not increase the theoretical maximum size of the memory, but it does double the maximum achievable size for the 256 Mb and 512 Mb parts.
Page 147: Table 64: Example For 128 Mbyte Cs Region With 4K Rows, 1K Columns, 128 Byte Interleave
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 64: Example for 128 MByte CS Region with 4K Rows, 1K Columns, 128 Byte Interleave Row Address Bits [26:15], Column Address Bits [14:9,6:5,4:3], Bank Address Bits [8:7] 00000000_00000111_11111111_10000000_00000000 Column 00000000_00000000_00000000_01111110_01100000 Bank 00000000_00000000_00000000_00000001_10000000 The previous examples show interleaving between the banks within a device. It is also possible to use interleave between chip selects on a channel.
Page 148: Choosing Interleave Parameters
In some cases using both channels may not be possible on the BCM1250 (for example if the system has a single DIMM slot then a two physical-bank DIMM is necessarily on a single channel), but both channels should be used if possible (to continue the example: a second DIMM slot should go on the other channel in preference to using the remaining two chip selects of the first channel).
Page 149 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The simple configuration with two channels each with one physical bank of memory provides a good illustration of the trade-offs involved. The most straightforward way to assign the channels is to have one cover address 0 to N-1 and the other address N to 2N-1. However, most of the time there is a reasonable degree of locality...
Page 150: Page Policy
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 This will give a good starting point and should give acceptable results in most systems. Modifications can then be made as a result of performance monitoring. OLICY The memory controller supports page mode access to the DDR SDRAMs, and provides several different policies for controlling page accesses.
Page 151: Supported Drams And Dimms
DDR and FCRAM parts are identical with the exception of pins 21, 22, and 23. On a DDR SDRAM these pins are WE#, CAS#, and RAS#, respectively. On the FCRAM, they become A14, A13, and FN (effectively WE#). The BCM1250 or BCM1125/H uses the same mapping when a channel is configured for FCRAM use, so: •...
Page 152: Dimms
DIMMS in the large memory system. This mode is enabled by setting the large_memory bit in the DRAM type field of the mc_drammode register. Application Note 1250- AN600-R “BCM1250 Big Memory System” describes the design and implementation of a board using the large memory extension.
Page 153: Ecc
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 • Initialization of the DRAMs must be done before the large_memory bit is set. It must be done for each of the real chip selects by stepping through the eight patterns of the chip select field in the mc_drammode register.
Page 154: Sdram Refresh
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 SDRAM R EFRESH The memory controller uses the SDRAM auto-refresh command to refresh the memory during normal operation. The refresh interval for a channel is set (in memory clocks) in the mc_clock_cfg register. In parts where the system_revision indicates PERIPH_REV3 or later this register also has fields to completely disable refresh (useful only during debugging, to avoid the scope being triggered by refresh cycles) or disable refresh for particular (i.e.
Page 155 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 When the part is reset the SDRAM channels are put in power-down mode with the clock stopped and CKE deasserted. Because CKE is deasserted all devices on the memory channel will place their outputs in a high impedance state, this will prevent multiple bus drivers as the channel starts up.
Page 156: I/O Control
The timing budget and electrical characteristics must be calculated for each board the BCM1250 or BCM1125/H is used on. In most cases the correct values for the I/O control registers will be calculated during board design and verified during bring up.
Page 157 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 70: Adjustment Percentages and Multiplier for Values of DLL M (Cont.) Adjustment% Multiplier Simulation Result for (M-8)*5% Simulation Result for 1+((M-8)*5%) 4'b1000 center 4'b1001 1.05 4'b1010 1.10 4'b1011 1.15 4'b1100 1.20 4'b1101 1.25 4'b1110 1.30 4'b1111 1.35...
Page 158: Figure 21: Timing Relationships Set By Dlls
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The drive position of the data relative to clock (t4 and t5) is controlled by the addr_skew parameter in the same way as the address, except the data changes on both edges of the clock. The data transition point is thus offset from both edges of the Mn_CLK by about 16% to 34% of the memory clock cycle time.
Page 159: Timing Parameter Guidelines
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 IMING ARAMETER UIDELINES The memory controller timing parameters must be configured to match the devices and board delays in the system. This section gives some guidelines for the parameters. During a read from memory the controller will use the DQS strobe supplied with each byte of the data to latch the four data-beats.
Page 160: Table 71: First Dqs Window Opening And Closing (Typical)
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 This figure shows where in time the first DQS edges must occur for various settings of the parameters [tCrD, tCrDh, tFIFO]. The following table describes the opening and closing of the windows for different parameter settings:...
Page 161 [n,1,2] for half-cycle CAS latencies. (Due to a performance bug systems with half-cycle CAS latencies using BCM1250 pass 1 prototype parts should use [n,0,2] if possible). There are three additional parameters r2wIdle, w2rIdle, and r2rIdle that address system timing concerns, specifically bus conflicts caused by the time delay between signals driven by the controller and signals driven by the SDRAMs.
Page 162: Performance Monitoring Features
Performance Counters” on page 61). Add discussion. ONITORING The functionality described in this section in previous releases of the BCM1250 manual was for the prototype chips only and is no longer available. The trace buffer in the SCD (See “Trace Unit” on page 70) should be used to monitor the ZBbus.
Page 163: Configuration Registers
Value of physical address bits [31:28] that should map to 3 (4th 256MB block) 39:32 probe_mode 8’b0 Reserved, Broadcom Use Only. Setting these bits to any value other than zero will result in UNDEFINED behavior and can cause the ECC lines to be continually driven regardless of the direction of the data transfer.
Page 164: Table 73: Memory Channel Configuration Register On Bcm1125/H
0: Generate a bus error data return 1: Generate a valid data return containing UNPREDICTABLE data. On the BCM1250 if this bit is set in either channel, bus errors will be disabled for all reads. force_seq 1’b0...
Page 165 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 73: Memory Channel Configuration Register on BCM1125/H (Cont.) mc_config_0 - 00_1005_1100 mc_config_1 - 00_1005_2100 Bits Name Default Description iob1_priority 1’b1 mc_config_1: If this bit is set reads from I/O bridge 1 will be given high priority (to reduce their latency).
Page 166: Table 74: Memory Clock Configuration Register
29:28 reserved 2’b0 Reserved ref_disable 1’b0 On BCM1250 prior to PERIPH_REV3: Reserved On other parts: If this bit is set refresh cycles are disabled. This can be useful during debugging, but must not be set in normal operation. dll_bypass 1’b0 Set this bit to bypass the DLLs.
Page 167: Table 75: Dram Command Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 74: Memory Clock Configuration Register (Cont.) mc_clock_cfg_0 - 00_1005_1500 mc_clock_cfg_1 - 00_1005_2500 Bits Name Default Description 61:56 dll_default 6’b010000 This is the value to use in place of the DLL output when DLL bypass is enabled.
Page 168: Table 77: Sdram Timing Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 76: DRAM Mode Register (Cont.) mc_drammode_0 - 00_1005_1140 mc_drammode_1 - 00_1005_2140 Bits Name Default Description 34:32 dram_type 3’b0 DRAM type: 000: JEDEC DDR (one DQS for every 8 DQ bits) 001: FCRAM 010: DDR SGRAM (one DQS for every 32 DQ bits)
Page 169: Table 79: Chip Select Start Address Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 77: SDRAM Timing Register (Cont.) mc_timing1_0 - 00_1005_1160 mc_timing1_1 - 00_1005_2160 Bits Name Range Default Description w2rIdle 1’b1 Number of idle cycles required for write to read turnaround. This bit must always be set. r2wIdle 1’b1...
Page 170: Table 81: Chip Select Interleave Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 81: Chip Select Interleave Register mc_cs_interleave_0 - 00_1005_11E0 mc_cs_interleave_1 - 00_1005_21E0 Bits Name Default Description reserved 5’b0 Reserved 24:5 interleave 20’b0 For mixed_cs mode single set bit should be written to this register in the bit position that should be used to select between the two chip selects in the interleaved portion.
Page 171: Table 84: Bank Address Bits Select Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 83: Column Address Bits Select Register (Cont.) mc_cs0_col_0 - 00_1005_1220 mc_cs1_col_0 - 00_1005_1280 mc_cs2_col_0 - 00_1005_12E0 mc_cs3_col_0 - 00_1005_1340 mc_cs0_col_1 - 00_1005_2220 mc_cs1_col_1 - 00_1005_2280 mc_cs2_col_1 - 00_1005_22E0 mc_cs3_col_1 - 00_1005_2340 Bits Name Description 63:21 reserved Must be zero.
Page 172: Table 86: Ecc Test Data Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 85: Chip Select Attribute Register (Cont.) mc_cs_attr_0 - 00_1005_1380 mc_cs_attr_1 - 00_1005_2380 Bits Name Default Description 47:34 reserved 14’h0 Must be zero. 49:48 cs3_page 2’b01 Page policy for Chip Select 3. (See Section: “Page Policy” on page 122.)
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Page 175: Section 7: Dma
_mac_ N _rx_ch_ M for receive channel M (0,1) of ethernet interface N (0,1 for the BCM1125/H and 0,1,2 for the BCM1250), and _mac_ N _tx_ch_ M for the transmit channels. The register names for the serial interfaces are generated by appending _ser_ N _rx and _ser_ N _tx for serial interface N (0,1).
Page 176: Figure 23: Dma Buffer
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Start Address size (in cache blocks) Offset Packet in bytes Length in bytes Aligned Aligned to 32 to 32 byte block byte block Figure 23: DMA Buffer Figure 23 shows a data buffer as used by the ethernet and serial interfaces (Data Mover buffers are the same but the alignment restrictions are removed).
Page 177: Figure 24: Dma Descriptor
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The DMA descriptor contains these parameters for each data buffer. A descriptor consists of two 64 bit double- words, dscr_a and dscr_b, that are stored in memory at consecutive locations aligned to a 16 byte boundary.
Page 178: Figure 25: Packet Spanning Three Buffers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Start Address size (in cache blocks) Offset Packet in bytes L1 (in bytes) Aligned Aligned to 32 to 32 byte block byte block Start Address size (in cache blocks) Offset Packet in bytes L2 (in bytes)
Page 179: Figure 26: Dma Descriptor Ring
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 INGS AND HAINS Each DMA engine works from a set of descriptors. These may be organized either as a ring or a chain. Size A Ring Base Buffer A Size B Descriptor 0 Buffer B Descriptor 1 .
Page 180 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 In a receive channel the interface flags the start of a packet when it sends data to the DMA engine. In a transmit channel the length field for one packet allows the DMA engine to directly determine when to expect the start of the next packet.
Page 181: Figure 27: Dma Descriptor Chain
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Size Buffer Descriptor Current Figure 27: DMA Descriptor Chain Figure 27 shows a descriptor chain. Each descriptor points to a single buffer, and contains a pointer to the next descriptor. Ownership of descriptors is passed in the same way as ring mode, the count refers to the number of valid descriptors.
Page 182: Unaligned Buffer Descriptor Format For Ethernet Dma
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 NALIGNED UFFER ESCRIPTOR FORMAT FOR THERNET The alignment restrictions in the standard DMA descriptors may be hard to work with in some existing systems and when a lot of scatter/gather operations are done to form packets for transmission. The DMA engine in the Ethernet/Packet Fifo Interface on parts with system revision indicating PERIPH_REV3 or greater supports a third descriptor format that allows arbitrary alignment of the start and end of buffers.
Page 183: Dma Coherence And Cache Options
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 This format is useful for scatter/gather operations, in particular when transmit packets are being composed and headers inserted or removed. Care must be taken since the format allows for very low performance settings: for example if all buffers are only 3 bytes then the overhead of fetching descriptors will completely dominate the data transfers.
Page 184: Dma Configurations
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 DMA C ONFIGURATIONS There are many ways that the DMA structure can be configured allowing use with many existing systems. The CPU should always use the cacheable coherent mode to access descriptors and buffers to allow the system to take care of the coherence and avoid the need for software to manage the L1 caches.
Page 185: Ethernet And Serial Dma Engines
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 DMA E THERNET AND ERIAL NGINES The Ethernet and serial DMA engines are identical except for using different per-packet options and status flags. Each channel works as described above using either a ring or a chain. The DMA engines have the restriction that neither the descriptors nor data buffers may be at an address serviced by I/O bridge 1, the system behavior is UNDEFINED if this is violated.
Page 186: Completion Interrupts
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The watermark status, which is used to raise an interrupt, is continually updated. If the number of descriptors falls below a watermark just as the CPU is doing a write to the count register to increase the number of descriptors owned by the DMA engine, the interrupt line may be briefly asserted but all status bits will be clear when the CPU has entered the interrupt service routine and reads the status register.
Page 187: Asic Mode Transfers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ASIC M RANSFERS The ethernet and serial interface receive DMA engines have a special "ASIC mode" that enables received packets to be passed through an ASIC on the HyperTransport fabric or PCI bus. This is in addition to just sending the packet by address to an I/O destination.
Page 188: Figure 30: Asic Mode Address Generation
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The pre_addr_en bit enables prepending of the dscr_a doubleword of the DMA descriptor to the data sent to the ASIC. If this bit is set then the offset in the DMA descriptor must be set to 8 (or greater than 8) and the asicxfr_size must be adjusted as outlined above.
Page 189: Figure 31: Sending The Whole Packet In Asic Mode
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Figure 31 shows a full packet being sent using ASIC mode. In this case the asicxfr_size is set to its maximum value (which is greater than the maximum packet size) ensuring the complete packet is sent to the ASIC.
Page 190: Figure 32: Sending A Packet Header In Asic Mode
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Figure 32 illustrates the ASIC mode being used to pass only the header of a packet (for example for classification). The asicxfr_size is set to the number of header cache blocks (typically 2, causing 64 bytes of header to be sent to the ASIC with no prepended descriptor or 1 causing 56 bytes of header to be sent with the prepended descriptor).
Page 191 ERIAL ONTROL EGISTERS The BCM1250 has MACs 0, 1 and 2. The BCM1125/H has MACs 0 and 1. Accesses made to the address range allocated to a nonexistant MAC may cause all MACs to exhibit UNPREDICTABLE behavior. Table 91: Ethernet and Serial DMA Configuration Register 0...
Page 192 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 91: Ethernet and Serial DMA Configuration Register 0 (Cont.) 47:32 high_watermark 16'b0 This specifies the high watermark for generating an interrupt to the CPU based on the number of descriptors. If the MAC receiver is asserting flow control and the number of descriptors rises above this watermark it will remove the flow control.
Page 193 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 92: Ethernet and Serial DMA Configuration Register 1 (Cont.) dma_config1_mac_0_rx_ch_0 - 00_1006_4808 dma_config1_mac_0_tx_ch_0 - 00_1006_4C08 dma_config1_mac_0_rx_ch_1 - 00_1006_4908 dma_config1_mac_0_tx_ch_1 - 00_1006_4D08 dma_config1_mac_1_rx_ch_0 - 00_1006_5808 dma_config1_mac_1_tx_ch_0 - 00_1006_5C08 dma_config1_mac_1_rx_ch_1 - 00_1006_5908 dma_config1_mac_1_tx_ch_1 - 00_1006_5D08 dma_config1_mac_2_rx_ch_0 - 00_1006_6808...
Page 194: Table 93: Ethernet And Serial Dma Descriptor Base Address Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 93: Ethernet and Serial DMA Descriptor Base Address Register dma_dscr_base_mac_0_rx_ch_0 - 00_1006_4810 dma_dscr_base_mac_0_tx_ch_0 - 00_1006_4C10 dma_dscr_base_mac_0_rx_ch_1 - 00_1006_4910 dma_dscr_base_mac_0_tx_ch_1 - 00_1006_4D10 dma_dscr_base_mac_1_rx_ch_0 - 00_1006_5810 dma_dscr_base_mac_1_tx_ch_0 - 00_1006_5C10 dma_dscr_base_mac_1_rx_ch_1 - 00_1006_5910 dma_dscr_base_mac_1_tx_ch_1 - 00_1006_5D10 dma_dscr_base_mac_2_rx_ch_0 - 00_1006_6810 dma_dscr_base_mac_2_tx_ch_0 - 00_1006_6C10...
Page 195: Table 96: Current Descriptor A Debug Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 96: Current Descriptor A Debug Register dma_cur_dscr_a_mac_0_rx_ch_0-00_1006_4820 dma_cur_dscr_a_mac_0_tx_ch_0-00_1006_4C20 dma_cur_dscr_a_mac_0_rx_ch_1-00_1006_4920 dma_cur_dscr_a_mac_0_tx_ch_1-00_1006_4D20 dma_cur_dscr_a_mac_1_rx_ch_0-00_1006_5820 dma_cur_dscr_a_mac_1_tx_ch_0-00_1006_5C20 dma_cur_dscr_a_mac_1_rx_ch_1-00_1006_5920 dma_cur_dscr_a_mac_1_tx_ch_1-00_1006_5D20 dma_cur_dscr_a_mac_2_rx_ch_0-00_1006_6820 dma_cur_dscr_a_mac_2_tx_ch_0-00_1006_6C20 dma_cur_dscr_a_mac_2_rx_ch_1-00_1006_6920 dma_cur_dscr_a_mac_2_tx_ch_1-00_1006_6D20 dma_cur_dscr_a_ser_0_rx - 00_1006_0420 dma_cur_dscr_a_ser_0_tx - 00_1006_04A0 dma_cur_dscr_a_ser_1_rx - 00_1006_0820 dma_cur_dscr_a_ser_1_tx - 00_1006_08A0 READ ONLY Bits Name Default...
Page 196 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 98: Current Descriptor Address Register (Cont.) dma_cur_daddr_mac_0_rx_ch_0 - 00_1006_4830 dma_cur_daddr_mac_0_tx_ch_0 - 00_1006_4C30 dma_cur_daddr_mac_0_rx_ch_1 - 00_1006_4930 dma_cur_daddr_mac_0_tx_ch_1 - 00_1006_4D30 dma_cur_daddr_mac_1_rx_ch_0 - 00_1006_5830 dma_cur_daddr_mac_1_tx_ch_0 - 00_1006_5C30 dma_cur_daddr_mac_1_rx_ch_1 - 00_1006_5930 dma_cur_daddr_mac_1_tx_ch_1 - 00_1006_5D30 dma_cur_daddr_mac_2_rx_ch_0 - 00_1006_6830 dma_cur_daddr_mac_2_tx_ch_0 - 00_1006_6C30...
Page 197: Table 100: Dma Descriptor First Doubleword
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 DMA D THERNET AND ERIAL ESCRIPTORS Table 100: DMA Descriptor First Doubleword dscr_a Bits Name Description offset The offset in the buffer that the header should start at. 39:5 a_addr The base address of the data buffer (cache block aligned). In ring mode this is the base address of the first data buffer.
Page 198: Table 102: Unaligned Buffer Format Dma Descriptor First Doubleword
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 102: Unaligned Buffer Format DMA Descriptor First Doubleword dscr_a Bits Name Description 39:0 addr The base address of the data buffer. 47:40 unused Unused. If extra_status is enabled the receive DMA engine will overwrite this field.
Page 199: Table 104: Status Flags For Ethernet Receive Channel
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 PTION AND ITS FOR THERNET Table 104: Status Flags for Ethernet Receive Channel Bits Name Description Flags Written to dscr_a size_a field if extra_status is enabled 47:40 dscr_cnt Number of descriptors used by this packet. If more than 255 descriptors were used to receive the packet then this field will be 0 and software must compute the actual number.
Page 200: Table 105: Option Flags For Ethernet Receive Channel
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 104: Status Flags for Ethernet Receive Channel (Cont.) Bits Name Description This bit is set to indicate the start of the packet. Software should ensure this bit is clear when it sets up the descriptor, the DMA controller will only set it when packet reception has been completed.
Page 201: Table 107: Option Flags For Ethernet Transmit Channel
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 107: Option Flags for Ethernet Transmit Channel Transmit Commands Bits Name Description pkt_mod This field indicates how the transmitter should modify the packet. 0000: Descriptor is not start of packet. 0001: Append CRC. 0010: Replace CRC.
Page 202: Table 108: Status Flags For Synchronous Serial Receive Channel
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ONTROL AND ITS FOR YNCHRONOUS ERIAL NTERFACE Table 108: Status Flags for Synchronous Serial Receive Channel Receive Status Flags Bits Name Description 55:51 reserved Reserved crc_error This bit is set if the received packet has a bad CRC.
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Page 204: Data Mover
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 OVER The Data Mover can perform transfers between arbitrary addresses. The source for a transfer can be either memory or an I/O device, and the destination of the transfer can be either memory or an I/O device. The alignment of the source and destination can differ, in which case the engine will participate in the MESI coherence protocol to ensure the correct merge is done at the start and end of the transfer.
Page 205 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Channels of the Data Mover can be individually enabled and reset. The reset bit should only be written when the channel is currently disabled or being disabled (i.e. it can be written with either the enable or disable command).
Page 206: Crc And Checksum Generators
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 HECKSUM ENERATORS In parts with system revision indicating PERIPH_REV3 or greater the Data Mover includes a programmable CRC generator and a checksum engine that computes the ones-complement checksum used by the TCP and UDP protocols. These can be used as part of a data copy or with the prefetch (null destination) parameter to read the data and generate the result without a copy.
Page 207: Crc Generation
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Note that if the prefetch flag is set no data will be moved and the destination address is used just to write the TCP sum if the append flag is set. If the Prefetch flag is clear then data will be moved as the checksum calculation is done and the TCP sum is appended if the append flag is set.
Page 208: Computation Sizes And Bandwidth
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 113 gives some example values for some common CRCs (in a particular use care will need to be taken with the final bit order). Table 113: Example CRC configurations crc_width crc_poly crc_init crc_txor crc_bit_order crc_xbit...
Page 209: Examples
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Examples The following examples illustrate uses of the checksum and CRC engine. These are intended to illustrate use of the data mover generators, in some cases it will be more efficient to do more processing of small buffers on the CPU rather than expending more effort on managing descriptors.
Page 210: Figure 34: Example 2 - Preparing An Iscsi Packet
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Example 2 illustrated in Figure 34 shows preparing an iSCSI packet for transmission. The example has a packet made up of a single buffer, although split buffers could also be used. Again, software must compute the pseudo-header sum and put it in the TCP header checksum field.
Page 211: Figure 35: Example 3 - Fragmenting An Iscsi Packet
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 if the checksum were appended in this descriptor it would be put on the end of the buffer after the CRC (software could do this and pick the final checksum from there). In the example this is solved using the observation that adding zeros does not change the checksum.
Page 212: Data Mover Control Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 OVER ONTROL EGISTERS Table 114: Data Mover Descriptor Base Address Register dm_dscr_base_0 - 00_1002_0B00 dm_dscr_base_1 - 00_1002_0B20 dm_dscr_base_2 - 00_1002_0B40 dm_dscr_base_3 - 00_1002_0B60 Read clears some bits Bits Name Default Description zero 4'b0 These bits must be zero.
Page 213: Table 116: Data Mover Descriptor Count Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 116: Data Mover Descriptor Count Register dm_dscr_count_0 - 00_1002_0B08 dm_dscr_count_1 - 00_1002_0B28 dm_dscr_count_2 - 00_1002_0B48 dm_dscr_count_3 - 00_1002_0B68 Bits Name Default Description 15:0 count 16'b0 This is the number of descriptors owned by the DMA engine. Reads will return the number of unused descriptors.
Page 214 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 119: Data Mover CRC/Checksum Definition Registers (Only if System Revision >= PERIPH_REV3) ctcp_def_0 - 00_1002_0B88 ctcp_def_1 - 00_1002_0B98 Bits Name Default Description 31:0 crc_txor 32'bx This value is XORed with the partial result of the CRC computation before the final result is written to memory.
Page 215: Table 121: Data Mover Descriptor First Doubleword
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 OVER ESCRIPTORS Table 121: Data Mover Descriptor First Doubleword dm_dscr_a Bits Name Description 39:0 dst_addr The destination address of the transfer (may be any alignment). un_dest This bit should be set for an uncached destination, and clear if the destination is cacheable coherent.
Page 216: Table 122: Data Mover Descriptor Second Doubleword
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 121: Data Mover Descriptor First Doubleword (Cont.) dm_dscr_a Bits Name Description 63:62 reserved Reserved Table 122: Data Mover Descriptor Second Doubleword dm_dscr_b Bits Name Description 39:0 src_addr The source address of the transfer (may be any alignment).
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Page 218: Section 8: Pci Bus And Hypertransport Fabric
The PCI bus and HyperTransport (formerly called “Lightning Data Transport” or “LDT”) fabric provide the main general expansion buses for the BCM1250 and BCM1125/H parts. PCI is the standard bus used for peripheral connection in many systems and there are a wide variety of peripheral devices that connect to it.
Page 219: Figure 36: Pci And Hypertransport Organization
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Figure 36 shows the physical and logical organization of the PCI and HyperTransport interfaces. Physical View Logical View ZBbus ZBbus Host Bridge IO Bridge 0 Bus 0 Device Device Device Device Interface Interface Bridge Bus 1...
Page 220: Pci And Hypertransport Address Range
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 YPER RANSPORT DDRESS ANGE This section describes how devices on the PCI bus and HyperTransport fabric (and any buses bridged from them) are mapped into the memory space. There are two complexities in the mapping. The first is supporting the different types of access that need to be done, and the second is supporting endian swapping when the part is running as a big endian system (both PCI and HyperTransport are little endian).
Page 221: Figure 37: Address Ranges For Cpu Access To Pci And Hypertransport
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The PCI and HyperTransport portions of the memory map are shown in Figure FF_FFFF_FFFF Reserved FA_0000_0000 PCI Full Access (match bit lane) F9_0000_0000 PCI Full Access (match byte lane) F8_0000_0000 HT Device Expansion Space (40 bit addressing, selectable endian policy)
Page 222: Memory Mapped Devices
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 EMORY APPED EVICES There is a 512MB region for mapping memory mapped PCI and HyperTransport devices. Logically this all maps to the PCI and a segment of it is bridged to the HyperTransport. (On the BCM1125 there is no HyperTransport interface and all accesses to this space are PCI accesses.) Thus the area is divided up into...
Page 223: Pci I/O Space
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 PCI I/O S PACE PCI, and for compatibility HyperTransport, has both memory space and I/O space corresponding to the standard and I/O instructions in the x86 architecture. Most PCI devices are mapped into memory space, as memory mapped I/O devices (indeed the PCI standard encourages this) but some use I/O space addresses.
Page 224 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 There is a reset time configuration bit southOnLDT (on generic bus IO_AD[21]) that sets whether the route to the southbridge is via the PCI bus or HyperTransport fabric. This is done as a hardware configuration option to allow use of the southbridge before the PCI bus and HyperTransport fabric have been configured (this is in line with section C.3 of the HyperTransport specification rev 0.17, and section E.3.1 of the HyperTransport...
Page 225 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Compatibility space routing is summarized in the pseudo-code below: if (00_4000_0000 <= zbaddr <= 00_7FFF_FFFF) pcildtaddr = zbaddr & DFFF_FFFF endian = zbaddr[29] ? match bit lanes : match byte lanes if (pcildtaddr < 00_4100_0000) /* Note after a[29] removal */...
Page 226: Hypertransport End Of Interrupt (Eoi) Signaling Space
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 For I/O space: if (00_4000_0000 <= zbaddr <= 00_7FFF_FFFF) ioaddr = (zbaddr & 1FF_FFFF) endian = zbaddr[29] ? match bit lanes : match byte lanes if (ioaddr < 000_8000) if ((ioaddr[24:16] == 0) && (((ioaddr[9:4]==3B) && (ioaddr[3:2]!=2'b11)) ||...
Page 227: Pci Full Access Space
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 In addition to generating EOI this space can be used to generate HyperTransport interrupt messages. If bits [4:2] of the address are not equal to 3'b111 (i.e. the message is encoding something other than an EOI) rather than sending a Posted Broadcast message the bridge will send a Posted Sized Byte Write with a count of zero, the COMPAT bit clear and a doubleword of zeros as byte masks (the extended destination bits from rev 1.01...
Page 228: Hypertransport Read Restrictions
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 YPER RANSPORT ESTRICTIONS The HyperTransport interface maps read requests from the ZBbus into read commands on the HyperTransport fabric. The interface supports all requests that can be generated by CPU instructions (reads of 1-8 bytes and 32 bytes) and any request that includes an aligned number of 32-bit words.
Page 229: Endian Policies
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 NDIAN OLICIES The system can be run either as a big endian system or as a little endian system. Both the PCI bus and HyperTransport fabric are little endian. When the part is running big endian there are two policies that are used for connecting to the interfaces.
Page 230: Big Endian System: Match Byte Lanes
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 NDIAN YSTEM ATCH ANES The match byte lanes endian policy will match the byte lanes of 32 bit values on either side of the interface. This preserves the memory address ordering between the ZBbus and PCI or HyperTransport. However, it will scramble the bit ordering.
Page 231: Big Endian System: Match Bit Lanes
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 NDIAN YSTEM ATCH ANES The match bit lanes endian policy will match the bit numbers of 32 bit values on either side of the interface. In byte lane terms this is an endian swap of the data. Consequently a 32 bit value that is written into a PCI register from the CPU will have the same interpretation.
Page 232: Viewing Endian Policy As An Optimization
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 As an example consider accessing control registers with the same layout as the standard PCI header (this layout is used only as a familiar one for the example, the interface does not allow 64 bit accesses in configuration space so this cannot be used directly).
Page 233: Table 123: Pci Base Address Register Use
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 This is an optimization because the endian swap is several instructions compared to the single OR (and in many cases all of the control registers need the swap so the base address of the control block can just be offset once;...
Page 234: Figure 41: Pci Bar0 Address Mapping Table
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Addresses on the PCI that match in BAR0 are mapped into internal addresses using a mapping table illustrated Figure 41 on page 206. This allows a PCI device to access any area of in the internal address map, and can be used to ensure PCI devices can only access specified memory areas.
Page 235 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 BAR2 and BAR3 provide access to the CPU mailbox registers (see Section: “Mailbox Registers” on page 46). The PCI device can read the current value of the mailbox and do writes to set bits in the mailbox, but it is not able to clear the mailbox.
Page 236 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Once the PCI interface has accepted a transaction that hits in one of the BARs (by asserting P_DEVSEL_L) it will complete or be terminated with a Target Abort. There are four classes of problems that will cause Target Abort: An error is detected on the PCI bus.
Page 237: Figure 42: Default Host Mode Memory Map From Pci Bus Master
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 DRAM 01_0000_0000 Maps to 00_D800_0000 BAR 5 Upper Memory (B) - 00_DFFF_FFFF Match bit endian policy With match bit endian policy 00_F800_0000 E000_0000 00_E000_0000 PCI/HT Config 00_DE00_0000 PCI/HT I/O Space BAR 5 00_DC00_0000 Upper Memory (B)
Page 238: Accessing The Sibyte From Hypertransport Devices
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 CCESSING THE YTE FROM YPER RANSPORT EVICES The mapping from HyperTransport addresses to those in the part is much simpler than from PCI. It is shown Figure HT Address SiByte Device FF_FFFF_FFFF FF_FFFF_FFFF Reserved (NxA) FD_FE00_0100...
Page 239 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The HyperTransport interface always runs as a host bridge, and has a PCI type 1 configuration header. The base and limit registers in the header define the region of the PCI/HyperTransport memory space that is allocated to devices on the HyperTransport fabric (these devices can be accessed by a system that uses 32 bit addresses).
Page 240: Force Isochronous Mode Address Range
The interface provides limited support for double-hosted HyperTransport chains. This is primarily intended for interconnection of two BCM1250s, two BCM1125Hs or a BCM1250 to a BCM1125H. The HT configuration registers are accessible from the HyperTransport fabric as device=0 function=0. At system startup one part must be designated the master, and the other the slave (this could be done by using the reset configuration resistors that are allocated for software use, or by having different bootstrap code on the two devices).
Page 241: Hypertransport Bounce Space
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Accesses from the ZBbus of one part to the F0_0000_0000 - F0_FFFF_FFFF region of the address map will be sent over the HyperTransport fabric, accepted by the second part and direct mapped to a PCI access on the second device.
Page 242: Accesses From The Sibyte To The Pci Or Hypertransport
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 CCESSES FROM THE YTE TO THE YPER RANSPORT The data path from the ZBbus to the PCI or HyperTransport is split into three sections. The interface to the ZBbus includes queues of requests and returning data. Inside the I/O bridge there are additional buffers in the routing path to the interface block.
Page 243 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The HyperTransport fabric uses split transaction reads and the interface supports 14 reads outstanding on the fabric. When a HyperTransport response arrives it is matched to the associated request and passes back through the RDR path. If a masked read (a read that is not a multiple of aligned 32-bit words) is encountered...
Page 244: Accesses From The Hypertransport To The Sibyte
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 CCESSES FROM THE YPER RANSPORT TO THE Figure 45 shows the queueing for DMA accesses from the HyperTransport fabric and PCI bus into the part. Queue up to 4 Queue up to 4 Queue Queue 1 Outstanding RDR...
Page 245: Accesses From The Pci To The Sibyte
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 CCESSES FROM THE TO THE The path for the PCI to access the part is shown in Figure 45 on page 216. It is similar to the HyperTransport flow. Writes from the PCI are always posted into the part, they flow through the queues shown in the figure.
Page 246: Figure 46: Pci Adaptive Retry Parameters
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 124: Adaptive Retry Delay Condition New Delay Before Retry Memory latency > max_tar_retry retry_delay = min_tar_retry retry_delay != min_tar_retry retry_delay = max_tar_retry AND max_tar_retry > Memory latency > nom_tar_retry retry_delay == min_tar_retry retry_delay = nom_tar_retry AND nom_tar_retry >...
Page 247: Peer-To-Peer Accesses
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 CCESSES The interface supports peer-to-peer accesses from devices on the PCI bus to devices on the HyperTransport fabric, and from devices on the HyperTransport fabric to devices on the PCI bus. Requests and data being transferred in this way do not travel on the ZBbus, they are directly routed through special buffers in the I/O Bridge 0.
Page 248: Figure 47: Buffers Used For Pci To Hypertransport Peer-To-Peer Accesses
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Figure 47 shows the queues used in peer-to-peer operations with a PCI master. Peer-to-peer writes will transfer exactly the number of bytes written and will always be posted to the HyperTransport fabric. They flow in their own channel from the PCI interface to the HyperTransport interface and may pass non-posted reads.
Page 249: Figure 48: Buffers Used For Hypertransport To Pci Peer-To-Peer Accesses
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 PCI B YPER RANSPORT ABRIC TO Requests received by the HyperTransport interface to any addresses that fall in the space allocated to the PCI memory space (regions A and C in Figure 37 on page 193) or that fall into the special double ended chain...
Page 250: Pci Arbiter
This section lists the main differences between the HyperTransport Specification Revision 0.17 and the interface implemented in the BCM1250 and BCM1125H. Since there was only limited distribution of the 0.17 specification, most readers will find the next section (differences from revision 1.03) more useful.
Page 251 The correct ordering of interrupts with respect to writes from the HyperTransport into the BCM1250 is maintained. An interrupt that follows a HyperTransport write will not be raised inside the BCM1250 until the write is visible inside the ZBbus coherency boundary.
Page 252: Hypertransport Differences From Revision 1.03 Specification
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 1.03 S YPER RANSPORT IFFERENCES FROM EVISION PECIFICATION This section compares the HyperTransport interface with the HyperTransport I/O Link Protocol Specification Rev 1.03 10/10/2001. This is the first specification released by the HyperTransport Consortium, the specification details and section numbers match the 1.02 release made by AMD. Comments are made by section number in the specification.
Page 253 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 4.4.2 Broadcast Message The only broadcast message the interface will generate is an EOI. No broadcast messages are accepted. 4.4.3 Flush, 4.4.4 Fence The interface will never generate a Flush or Fence command. They will be accepted and Flush will result in a TgtDone return.
Page 254 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 6.1 Upstream I/O Ordering The interface follows the ordering rules through the HyperTransport Interface into the I/O Bridge. 6.2 Host Ordering Rules The ordering rules are maintained into the ZBbus domain, which has a different set of rules.
Page 255 10/21/02 7.5.3.3 Host Interface Command Bits The pass 2 BCM1250 does not implement the fields that are new in the revision 1.02 specification: Device Number, Chain Side, Host Hide, Act as Slave, Drop on Uninit. Interface revision 3 and greater, used for the BCM1125H and later versions of the BCM1250, includes these.
Page 256 HyperTransport link or PCI and does not decode to a legal address within the BCM1250. It is also flagged and the transaction dropped, for a posted operation if the srcid is zero (i.e. it has come from the other host on a double-hosted chain) and the destination is an address on the HyperTransport link.
Page 257: Table 125: Error Routing Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 10.1.7 Response Errors A response received without a matching source tag (or as a result of a response to a WrSized request) is reported as a SrcTagError in the HyperTransport Error Status Register (Table 153 on page...
Page 258 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 12.2 Low Level Link Initialization and Table 54 Values of CTL and CAD During Link Initialization Sequence The transmit side will generate 512 cycles with CTL and CAD as zero before asserting CAD and the receive side will accept 512+M cycles. This matches both the older versions of the spec...
Page 259: Ordering Rules
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 E.3 Subtractive Decode Subtractive Decode is discussed in the “The SouthBridge, VGA and Subtractive Decode” on page 195. F.1 Interrupts The interface follows the x86 interrupt mechanism as outlined in Section: “HyperTransport Interrupts” on page 48. Interrupt messages and EOI are generated by software as described in Section EOI Signalling Space on Section: “HyperTransport End Of Interrupt (EOI) Signaling...
Page 260: Using The Pci In Device Mode
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 SING THE EVICE The part can be used in PCI Device Mode in a couple of different situations. The main one is when it is used as a PCI device on an option card and the second is when the PCI is used to connect several parts in a system.
Page 261: Table 126: Pci Csr Access Rules
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 any PCI access will be issued with a retry. Software on the part should do initial configuration of the map registers and set the subsystem information before writing a zero to the rd_host bit and flush the write to the interface by following it with a dummy read that will return UNPREDICTABLE data.
Page 262: Figure 49: Configuration Space Address
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ONFIGURATION OF YPER RANSPORT The PCI bus and HyperTransport fabric both require configuration before use. This is normally done by the startup firmware, but may also be done by the operating system as it starts. There is usually a "PCI-BIOS"...
Page 263 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Accesses to the configuration range with bus 0 device 0 and bus 0 device 1 will be directed to the internal configuration registers for the PCI and HyperTransport interfaces. Once the CPU has performed a series of writes to the internal configuration registers it should read back at least one.
Page 264: Hypertransport Target Done Counter
YPER RANSPORT If a BCM1250 or BCM1125H system does not use the HyperTransport interface the mem_base, mem_limit, io_base and io_limit registers of the HT bridge must still be programmed. This configures a shadow copy of these registers that is by default UNPREDICTABLE. The mem_limit should be set to be lower in address than the mem_base.
Page 265 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 127: PCI Interface Configuration Header (Type 0) (Cont.) Register Bits Offset Description Class Code Rev Id Class is a host bridge, revision reflects the R/O 060000 R/O xx interface revision code. The revision code is: 1 - for early prototype BCM1250s.
Page 266 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 127: PCI Interface Configuration Header (Type 0) (Cont.) Register Bits Offset Description 44-80 Map Entry Base Address Flags The address mapping table for BAR0, described R/W 000000 R/W 00 Table 134 on page 242. Error Address...
Page 267: Table 128: Pci Command Register - Offset 4 Bits [15:0]
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 128: PCI Command Register - Offset 4 Bits [15:0] Bits Name Default Description IoSpaceEn R/O 1’b0 I/O Space Enable. This bit is always zero. The bridge never accepts I/O space accesses from the PCI bus.
Page 268: Table 130: Pci Latency Timer - Offset 0C Bits [15:8]
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 129: PCI Status Register - Offset 4 Bits [31:16] (Cont.) Bits Name Default Description SigdTgtAbort This bit is set when the bridge is the target of a PCI transaction and signalled a 0’b0 Target Abort. If this bit is set the PCI error interrupt is asserted. It is cleared by software writing a 1.
Page 269: Table 133: Pci Feature Control Register - Offset 40 Bits [31:16]
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 133: PCI Feature Control Register - Offset 40 Bits [31:16] Bits Name Default Description bar4_en R/W 1’b1 This bit must be set to enable accesses through BAR 4 in Host Mode. (default enabled). bar5_en R/W 1’b1 This bit must be set to enable accesses through BAR 5 in Host Mode.
Page 270: Table 136: Pci Inta Control Register - Offset 90 Bits [31:0]
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 135: PCI Additional Status and Control Register - Offset 88 Bits [31:0] (Cont.) Bits Name Default Description RetryErr R/C 1’b0 Set when a transfer is aborted because a read was retried more than the RetryTimeout (See Table 132 on page 241).
Page 271: Table 139: Pci Bypass Control Register - Revid >= 3 Offset A8 Bits [31:0]
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 138: PCI Adaptive Extend Register - Offset 98 Bits [31:0] (Cont.) Bits Name Default Description dis_memrd_be 1'b0 This bit should be zero for normal operation. If set the byte enables will always be all set for read transactions.
Page 272: Table 140: Hypertransport Configuration Header (Type 1)
Register Bits Offset Description 24 23 16 15 Device Id Vendor Id Identifies the device as a Broadcom SiByte family R/O 0002 R/O 166D 8 bit HyperTransport interface. Status (See Command (See As defined in the HyperTransport specification. Table 142 on page...
Page 273 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 140: HyperTransport Configuration Header (Type 1) (Cont.) Register Bits Offset Description 24 23 16 15 Reserved R/O 000000 Cap Ptr R/O Points to HyperTransport capability registers. ROM base address R/O 0 The HyperTransport bridge does not support an expansion ROM.
Page 274: Table 141: Hypertransport Bridge Command Register - Offset 4 Bits [15:0]
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 140: HyperTransport Configuration Header (Type 1) (Cont.) Register Bits Offset Description 24 23 16 15 70-C4 Reserved R/O Unpredictable Reserved TxBufCountMax (See Table 157 on page 255) Transmit buffer control register. R/W 00FFFFFF CC-D8 Reserved R/O Unpredictable...
Page 275: Table 142: Hypertransport Bridge Primary (Zbbus) Status Register - Offset 4 Bits [31:16]
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 142: HyperTransport Bridge Primary (ZBbus) Status Register - Offset 4 Bits [31:16] Bits Name Default Description reserved R/O 4’b0 Reserved CapList R/O 1’b1 Always set. There is a capabilities list pointed to by the pointer register.
Page 276: Table 144: Hypertransport Bridge Control Register - Offset 3C Bits [31:16]
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 144: HyperTransport Bridge Control Register - Offset 3C Bits [31:16] Bits Name Default Description ParErrRespEn R/O 1’b0 This bit applies to PCI bridges only. For a HyperTransport bridge it is read only and always returns a zero.
Page 277: Table 146: Hypertransport Link Control Register - Offset 44 Bits [15:0]
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 145: HyperTransport Command Register - Offset 40 Bits [31:16] (Cont.) Bits Name Default Description Reserved R/O 1’b0 On interface RevID 1 and 2 this field is reserved. RevID>=3 On interface with RevId 3 and greater this bit reads as a 0 from the ZBbus side and ChainSide R/W 1’bx...
Page 278: Table 147: Hypertransport Link Configuration Register - Offset 44 Bits [31:16]
When a CRC error is received on the incoming link the bridge will set the bit in this field corresponding to the byte lane that had the error. The BCM1250 only supports an 8-bit link, so bit [8] is the only one that will ever be set.
Page 279: Table 149: Hypertransport Sri Command Register - Offset 50 Bits [31:16]
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 149: HyperTransport SRI Command Register - Offset 50 Bits [31:16] Bits Name Default Description SipReady R/W 1’b0 System Initialization Process Ready. This bit should be set by software when the SRI initialization process is complete. The LDT bridge will be held in reset until this bit is set.
Page 280: Table 151: Hypertransport Isochronous Ignore Mask - Offset 60Bits [31:0]
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 151: HyperTransport Isochronous Ignore Mask - Offset 60Bits [31:0] Bits Name Default Description reserved R/W 1’b0 Reserved 31:1 isocMask R/W 31’b0 This specifies the mask of bits that are ignored when the comparison is done to force the iscochronous bit.
Page 281: Table 153: Hypertransport Error Status Register - Offset 68 Bits [31:24]
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 153: HyperTransport Error Status Register - Offset 68 Bits [31:24] Bits Name Default Description ProtoErr R/C 1’b0 This bit will be set if a protocol error is detected on the incoming link. Software may clear this bit by writing a 1 to it.
Page 282: Table 157: Hypertransport Sri Transmit Buffer Count Max Register - Offset C8 Bits [31:0]
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 156: HyperTransport Additional Status Register - Offset 70 Bits Name Default Description tgt_done Target Done Counter. This value is incremented every time a Target Done 8'b0 acknowledgement is received from the fabric. These will happen as a result of the NonPosted writes done in configuration space.
Page 283: Figure 50: Hypertransport Interface Clocks And Fifos
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 YSTEM ESET NITIALIZATION OF THE YPER RANSPORT NTERFACE There are a number of parameters that must be configured in the HyperTransport interface before the HyperTransport link can come out of reset and the link initialization described in the HyperTransport Specification can start.
Page 284: Configuration Flags In The Sricmd Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Configuration Flags in the SriCmd Register There are three flags in the SriCmd register. Two of these should be set at the start of initialization. The ReduceSyncZero flag should only be set during debugging; it reduces the number of bit times of zeros during link initialization from the standard 512 to 128.
Page 285: Receive Pointer Margin Control In Sricmd Register
The transmitter registers work similarly. Bits in the Numerator indicate that data should be inserted into the transmit FIFO from the internal clock. In the BCM1250 or BCM1125H, the clock ratio is fixed to 1/4. Data is inserted into the FIFO 8 bytes wide on the internal clock and removed byte wide on each edge of the HyperTransport transmit clock.
Page 286: Transmit Pointer Initial Offset In The Sricmd Register
LDTINT In asynchronous mode the RxMargin field should be programmed to twice the number of receive clock cycles for the data to settle. The settle time recommended for the BCM1250 or BCM1125H is 7ns, so in asynchronous mode: RxMargin = 2*7ns*f...
Page 287: Buffer Control: Txbufcountmax And Databufalloc
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Buffer Control: TxBufCountMax and DataBufAlloc The Transmit Buffer Count Max register sets the maximum number of buffers the transmitter will use in each of the six buffer classes described in the HyperTransport Specification. The classes (Posted Command, Posted Data, NonPosted Command, NonPosted Data, Response and Response Data) match the buffers in the receiver and fields in the NOP flow control packet.
Page 288 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The registers that make up the HyperTransport Bridge header are reset by both system resets and are unaffected by link reset with the following exceptions: The HyperTransport SRI Command Register is reset on system cold reset and persistent across system warm reset.
Page 289 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 This Page is left blank for notes B r oadco m C orp or ati on Document 1250_1125-UM100CB-R Section 8: PCI Bus and HyperTransport Fabric Page...
Page 290 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 This Page is left blank for notes B r oadco m C orp or ati on Page Section 8: PCI Bus and HyperTransport Fabric Document 1250_1125-UM100CB-R...
Page 291: Section 9: Ethernet Macs
The MAC interfaces can be replaced by Packet FIFO interfaces that are 16-bits wide in each direction. Pins from MAC E0 and E1 are reassigned to Packet FIFO interface F0 on the BCM1250 or F on the BCM1125/H, and on the BCM1250 pins from all three MACs are reassigned to Packet FIFO interface F1. Selection between Ethernet and Packet FIFO operation is done by software.
Page 292: Interface Overview
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 NTERFACE VERVIEW Figure 51 shows the block diagram of a single Ethernet interface. The interface to the system bus is provided through I/O Bridge 1. This allows the CPU to access the interface control registers, the RMON statistical counters and the DMA control interface.
Page 293 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The DMA controllers are described in Section7: “DMA” on page 147. On the transmit side there are two DMA channels which are serviced using a weighted round robin algorithm. In the receive direction there are also two channels, the packet header is used to select which will be used for delivery.
Page 294: Protocol Engine And Gmii/Mii
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 GMII/MII ROTOCOL NGINE AND The Ethernet MAC engine performs all the MAC layer processing needed to comply with the IEEE 802.3 standard at 10 Mbps, 100 Mbps and 1000 Mbps. It interfaces to the receive and transmit FIFOs to move data into and out of the system, and connects to an external physical layer interface (PHY) using the standard MII (media independent interface) connection for 10/100 Mbps operation and the GMII for gigabit operation.
Page 295: Ethernet Frame Format
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 THERNET RAME ORMAT The Ethernet frame format is shown in Figure Standard Frame Previous Destination Source Type Preamble SFD Data CRC IFG Frame Address Address Length 46-1500 ifg_tx Min Packet Size Max Packet Size ifg_thrsh Ignore...
Page 296: Table 160: Ethernet Frame Fields
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The frame is broken up into the following fields: Table 160: Ethernet Frame Fields Name Description Inter-frame Gap. This is the period that the link is idle between frames. The size of the gap used by the MAC is programmable. The ifg_tx parameters in the mac_frame_cfg register sets the gap that will be used after reception and transmission of a packet.
Page 297: Prepended Header Frame Format
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 REPENDED EADER RAME ORMAT In devices with system revision indicating PERIPH_REV3 or greater the MAC interface supports a modified frame format that has an additional header prepended before the Ethernet frame. The CRC can be set to cover the prepended header and Ethernet frame or just the Ethernet frame (or a combination).
Page 298: Protocol Engine Configuration
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ROTOCOL NGINE ONFIGURATION The basic encapsulation parameters are set in the mac_frame_cfg register. This allows configuring of the inter-frame gap, maximum backoff time, slot size, minimum frame size and maximum frame size. This must be programmed to the correct values for IEEE 802.3 operation at 10 Mbp/s and 100 Mbp/s. For gigabit operation the slot_size is automatically increased to 512 byte times (rather than 512 bit times) but software must half the IFG values;...
Page 299: Figure 54: Transmit Fifo Thresholds
Gbit/s operation the data lines are clocked at 125 MHz so the clock is forwarded with the data. In this case the reference clock input is used (on the BCM1250, the REFCK01 pin is for interfaces E0 and E1, and the REFCK2 pin for interface E2;...
Page 300: Table 161: Transmission Error Conditions
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 In half-duplex operation the Ethernet protocol expects collisions to occur, and relies on them to share access to the transmission medium. These collisions will only occur at the start of packet transmission, and the interface will backoff for a random period before retrying the transmission. The maximum backoff time is exponentially increased (up to a maximum 1024 slot times) each time a collision is encountered.
Page 301: Transmit Path
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 161: Transmission Error Conditions (Cont.) Bit to Set for Error Description Automatic Retry CRC error None The transmitted CRC is compared to the CRC that was computed over the frame, and Cannot be retried this error is raised if they differ. If the interface is automatically appending the CRC, then this error will never happen.
Page 302: Receiver Operation
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ECEIVER PERATION ECEIVER ONFIGURATION The receive fifo is a 64 bit wide fifo with 64 entries. When the FIFO contains data it will signal the DMA engine to request emptying. The rx_rd_thrsh field in the mac_thrsh_cfg register sets the number of valid entries that must be in the FIFO to request emptying.
Page 303: Table 162: Receiver Error Conditions
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Automatic discard can be triggered by any error that happens (FCS error, code error, dribble error, runt error, oversize error or length error) while the FIFO is locked (i.e. less than the number of entries set by rx_rl_thrsh have been written into the receive FIFO after the start of a given packet).
Page 304: Receive Path
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 162: Receiver Error Conditions (Cont.) Bit to set for Error Description automatic dropping Underflow None An underflow error is reported when the receive DMA engine (or external agent in direct mode) reads the receive FIFO when it is empty. The data returned is UNPREDICTABLE and the FIFO pointers will not change.
Page 305: Destination Address Filtering
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ESTINATION DDRESS ILTERING The MAC will filter received packets based on their Ethernet destination address. Packets that pass the filter are received, those that do not are never delivered to the DMA engine. mac_hash7 mac_hash6 mac_hash5...
Page 306 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 There are five components to the filter. Broadcast packet detection. Broadcast packets are either all accepted or all rejected. Exact match. The incoming packet address is compared to eight addresses (which may be unicast or multicast addresses), if it matches any of them then the packet is accepted, otherwise it is rejected.
Page 307 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The value for the hash filter for a particular Ethernet address may be computed using the mchash macro and standard CRC generator given in the following code: /******************************************************************** * eth_hwcrc32(buf,len) Calculate a CRC-32 of the specified bytes.
Page 308: Figure 57: Receive Channel Selection
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 DMA C ECEIVE HANNEL ELECTION If a packet is accepted by the address filter the received DMA channel is selected. This is done by extracting eight bits out of the first 128 bytes received (if the rx_rl_thrsh threshold is set smaller than 128 then the eight bits must be in the rx_rl_thrsh bytes), and using them to lookup a two bit number in a small table formed using the mac_chup and mac_chlo registers.
Page 309: Packet Type Identification
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The receive channel selection is used in the same way in Packet FIFO mode. In devices where the system revision indicates PERIPH_REV3 or greater the 8 bit index into the channel number table can be formed from two four bit fields extracted from the packet. The split_ch_en bit in the mac_cfg register enables this feature.
Page 310: Ipv4 Header Checksum
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 EADER HECKSUM The receiver will check packets for an IPv4 header with no options and a correct header checksum. The iphdr_offset field in the mac_adfilter_cfg register sets the offset into the received packet that the header starts (this will normally be 15, since the IP header will start after the Ethernet header, but it can be adjusted to allow encapsulation headers to be skipped).
Page 311: Flow Control
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ONTROL The MAC supports flow control in both full-duplex and half-duplex modes. In full-duplex mode pause frames are used to request the peer to stop sending for a particular length of time. In half-duplex mode back-pressure is applied by forcing the physical layer into not allowing transmissions.
Page 312: Table 165: Pause Frame Options
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 In full-duplex mode the reception of a valid Pause Frame always suspends transmission at the end of the packet currently being sent, transmission will be resumed after the requested pause time unless another flow control packet is received. Pause frames will be detected if their destination address matches the address in the mac_ethernet_addr register or the multicast address 01-80-C2-00-00-01 and the packet type matches the MAC Control type (88_08) and he pause frame opcode (00_01) is found.
Page 313: Interrupts
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 165: Pause Frame Options (Cont.) ch_base Ch 0 Ch 1 fwdpause_en _fc_en fc_pause_en fc_pause_en Description Software pause frames. The pause frame will be received by software which may use the cpu_pause_en bit to pause channels, or may use it to cause discard from or reordering of internal queues.
Page 314: Management Interface To Phy
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ANAGEMENT NTERFACE TO There is a simple serial management interface between the MAC and the PHY device (or devices). It supports up to 32 PHY chips (although some PHY devices attach special meaning to address 0) each of which have 32 16-bit registers.
Page 315: Figure 59: Mdio Flows
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Figure 59 shows the flow for the main loop for sending and reading bits. Read Bits Write Bits Single Write to mac_mdio Single Write to mac_mdio mdc = 1 mdc = 0 mdio_out = bit to send...
Page 316: Rmon Counters
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The management protocol is shown in Table 166. This shows the two sides of the read (the MAC request and the PHY reply) and the full sequence sent by the MAC for a write. Bits are marked Z where the line is not being driven.
Page 317 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 167: RMON Counters (Cont.) Number (offset from Counter Description 00_1006_0000) Tx FCS Error Counter This Counter counts the total number of packets transmitted by the MAC with _0 - +4020 FCS error. This can only happen when MAC is not appending the CRC to the _1 - +5020 transmitted packet.
Page 318 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 167: RMON Counters (Cont.) Number (offset from Counter Description 00_1006_0000) Rx Good Packet This Counter counts the total number of good packets received (packets with _0 - +40A0 Counter no errors) by the MAC. _1 - +50A0...
Page 319: Packet Fifo Interfaces
GMII or 8 bit Fifo E0_ GMII or 8-bit Fifo E1_ One 16-bit Packet Fifo 16-bit Packet Fifo F_ The valid combinations for a BCM1250 are: • Interface 0 in 16-bit Packet mode, Interface 1 disabled, Interface 2 in Ethernet mode. •...
Page 320: Table 169: Bcm1250 Ethernet/Fifo Pin Usage
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The pin mapping is summarized in the following table: Table 169: BCM1250 Ethernet/Fifo Pin Usage E0_ pins E1_ pins E2_ pins All Interfaces Ethernet or 8-bit Fifo GMII or 8-bit Fifo E0_ GMII or 8-bit Fifo E1_...
Page 321: Flow Control In Encoded Packet Fifo Modes
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Flow Control In Encoded Packet FIFO Modes Flow control is available in the encoded packet fifo modes. In addition to the DMA descriptor based flow control there is a link level flow control. The transmitter can be controlled by the COL input in 8 bit mode and the TXFC input in 16 bit mode (note that these are the same physical pin).
Page 322: Figure 60: 8-Bit Packet Fifo Gmii Style
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 There are four formats that are available for the 8 bit Packet FIFO to signal data validity and packet boundaries. In all cases data and control signals are sampled on the rising edge of the clock. On the transmit side the GMII...
Page 323: Figure 61: 8-Bit Packet Fifo Encoded Style
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 FIFO NCODED ACKET Encoded mode, shown in Figure 61, uses the control lines to signal the four states that can be associated with the data. This mode should be used for packet data where there can be invalid bytes between the start and end of packet marks.
Page 324: Figure 62: 8-Bit Packet Fifo Sop Style
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 SOP F FIFO LAGGED ACKET SOP flagged Packet FIFO mode uses one control line as a data valid signal and the other to flag start of packet. The end of packet is one cycle before the SOP or whenever the data goes invalid (this extra EOP is required to push out the last data at the end of a valid sequence).
Page 325: Figure 63: 8-Bit Packet Fifo Eop Style
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 EOP F FIFO LAGGED ACKET EOP flagged Packet FIFO mode uses one control line as a data valid signal and the other to flag end of packet. The start of packet is one cycle after an end of packet, or the first data after the valid signal has risen. Any...
Page 326: 16-Bit Packet Fifo Operation
ASIC. On the BCM1250, there are two Packet FIFO interfaces. On the BCM1125/H there is one. Interface F0 (F on the BCM1125/H) replaces the Ethernet MACs E0 and E1, and reuses pins from both. It uses the DMA controller associated with interface E0.
Page 327: 16-Bit Encoded Packet Fifo
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 TXC/RXC[2] is used to indicate the validity of the upper 8-bits of data. It should be the same as TXC/RXC[0] except for the final data in a packet that has an odd number of bytes. Table 174: Codes for 16-Bit GMII Style Packet FIFO...
Page 328: Restrictions When Resetting The Interface
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 175: Codes for 16-Bit Encoded Bypass Mode TXC/RXC[2:0] Start of Packet, 2 Bytes Valid End of Packet, 2 Bytes Valid Middle of Packet, 2 Bytes Valid In this mode flow control is provided in each direction. Transmit flow control is input on the TX_FC pin, when this is asserted the interface will stop sending data (and drive the data not valid control code) two rising clock edges later.
Page 329: Mac Registers
Default Description ss_tmode 1'b0 This bit must always be zero for normal operation (Broadcom Use Only test bit). tx_hold_sop_en 1'b0 When this bit is set the interface will retain the first few bytes of each transmitted packet in the transmit FIFO. This enables the interface to automatically retry any packet that encounters an error during the initial part of its transmission.
Page 330 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 176: MAC Configuration Registers (Cont.) mac_cfg_0 - 00_1006_4100 mac_cfg_1 - 00_1006_5100 mac_cfg_2 - 00_1006_6100 This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description tx_pause_cnt 3'b0 Transmit pause count. This field sets the number of slot times pause that will be requested when the interface transmits a pause frame.
Page 331 Used in Ethernet and Packet FIFO modes. ss_en 1'b0 This bit must always be set. (Broadcom Use Only debug bit). (It defaults to 0 so software should be sure to set it before starting the MAC.) Used in Ethernet and Packet FIFO modes.
Page 332 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 176: MAC Configuration Registers (Cont.) mac_cfg_0 - 00_1006_4100 mac_cfg_1 - 00_1006_5100 mac_cfg_2 - 00_1006_6100 This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description bypass_fcs_chk 1'b0 If this bit is set then the interface will perform the FCS check on packets received in Packet FIFO mode.
Page 333: Table 177: Mac Enable Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 177: MAC Enable Registers mac_enable_0 - 00_1006_4400 mac_enable_1 - 00_1006_5400 mac_enable_2 - 00_1006_6400 This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description rxdma_en 2'b0 Receive DMA channel enable. Must be set to enable a channel.
Page 334: Table 179: Mac Fifo Threshold Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 179: MAC FIFO Threshold Registers mac_thrsh_cfg_0 - 00_1006_4108 mac_thrsh_cfg_1 - 00_1006_5108 mac_thrsh_cfg_2 - 00_1006_6108 This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description tx_wr_thrsh 7'b0 Transmit FIFO write threshold. Sets the number of free 64 bit entries the transmit FIFO must have before it signals that space is available.
Page 335: Table 180: Mac Frame Configuration Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 180: MAC Frame Configuration Registers mac_frame_cfg_0 - 00_1006_4118 mac_frame_cfg_1 - 00_1006_5118 mac_frame_cfg_2 - 00_1006_6118 This register is only used in both Ethernet mode no fields apply for Packet FIFO modes Bits Name Default Description ifg_rx 6'b0 System Revison <...
Page 336 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 180: MAC Frame Configuration Registers (Cont.) mac_frame_cfg_0 - 00_1006_4118 mac_frame_cfg_1 - 00_1006_5118 mac_frame_cfg_2 - 00_1006_6118 This register is only used in both Ethernet mode no fields apply for Packet FIFO modes Bits Name Default Description...
Page 337: Table 181: Mac Vlan Tag Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 181: MAC VLAN Tag Registers mac_vlantag_0 - 00_1006_4110 mac_vlantag_1 - 00_1006_5110 mac_vlantag_2 - 00_1006_6110 This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description 31:0 32'b0 VLAN tag. This 32 bit tag is inserted into the packet after the destination and source Ethernet addresses if the packet is marked for VLAN tag insertion.
Page 338 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 182: MAC Status Registers (Cont.) mac_status_0 - 00_1006_4408 mac_status_1 - 00_1006_5408 mac_status_2 - 00_1006_6408 READ ONLY - Reading this register will clear all latched bits This register is used in both Ethernet and Packet FIFO modes...
Page 339 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 182: MAC Status Registers (Cont.) mac_status_0 - 00_1006_4408 mac_status_1 - 00_1006_5408 mac_status_2 - 00_1006_6408 READ ONLY - Reading this register will clear all latched bits This register is used in both Ethernet and Packet FIFO modes...
Page 340: Table 183: Mac Status 1 Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 182: MAC Status Registers (Cont.) mac_status_0 - 00_1006_4408 mac_status_1 - 00_1006_5408 mac_status_2 - 00_1006_6408 READ ONLY - Reading this register will clear all latched bits This register is used in both Ethernet and Packet FIFO modes...
Page 341: Table 185: Mac Interrupt Mask Registers
Description 63:0 status 64'hx Status for fifo and counts (Broadcom Use Only) Table 187: MAC Receive Address Filter Exact Match Registers mac_addr0_0 - 00_1006_4280 mac_addr0_1 - 00_1006_5280 mac_addr0_2 - 00_1006_6280 mac_addr1_0 - 00_1006_4288 mac_addr1_1 - 00_1006_5288 mac_addr1_2 - 00_1006_6288 mac_addr2_0 - 00_1006_4290 mac_addr2_1 - 00_1006_5290 mac_addr2_2 - 00_1006_6290...
Page 342: Table 189: Mac Receive Address Filter Hash Match Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 188: MAC Receive Address Filter Mask Registers (Only if System Revision >= PERIPH_REV3) mac_admask0_0 - 00_1006_4218 mac_admask0_1 - 00_1006_5218 mac_admask0_2 - 00_1006_6218 mac_admask1_0 - 00_1006_4220 mac_admask1_1 - 00_1006_5220 mac_admask1_2 - 00_1006_6220 This register is used in both Ethernet and Packet FIFO modes...
Page 343: Table 191: Mac Packet Type Configuration Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 191: MAC Packet Type Configuration Registers mac_type_cfg_0 - 00_1006_4210 mac_type_cfg_1 - 00_1006_5210 mac_type_cfg_2 - 00_1006_6210 This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description 15:0 type0 16'b0 If a received packet has this packet type the receive descriptor will be written with type = 3’b100.
Page 344 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 192: MAC Receive Address Filter Control Registers (Cont.) mac_adfilter_cfg_0 - 00_1006_4200 mac_adfilter_cfg_1 - 00_1006_5200 mac_adfilter_cfg_2 - 00_1006_6200 This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description allm_en 1’b0 When this bit is set all multicast packets are accepted. When it is clear multicast packets will only be accepted if they match in the Exact or Hash filters.
Page 345: Table 193: Mac Receive Channel Select Map Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 193: MAC Receive Channel Select Map Registers mac_chlo0_0 - 00_1006_4300 mac_chlo0_1 - 00_1006_5300 mac_chlo0_2 - 00_1006_6300 mac_chlo1_0 - 00_1006_4308 mac_chlo1_1 - 00_1006_5308 mac_chlo1_2 - 00_1006_6308 mac_chlo2_0 - 00_1006_4310 mac_chlo2_1 - 00_1006_5310 mac_chlo2_2 - 00_1006_6310 mac_chlo3_0 - 00_1006_4318 mac_chlo3_1 - 00_1006_5318 mac_chlo3_2 - 00_1006_6318...
Page 346 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 This Page is left blank for notes B r oadco m C orp or ati on Page Section 9: Ethernet MACs Document 1250_1125-UM100CB-R...
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Page 348: Section 10: Serial Interfaces
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Se ction 10: Ser ia l Inte rfac es NTRODUCTION The part incorporates two identical serial ports that provide full-duplex interfaces to a variety of serial devices. Each port is separately configured, and can be run as an asynchronous serial link from 1200 baud to 5 Mbaud or a synchronous serial link at up to 55 Mbps.
Page 349: Table 196: Baud Rate Counter Values
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 SYNCHRONOUS The asynchronous interface is provided using a DUART. The two channels are separately programmable and each has its own baud rate generator. Each channel has a 16 byte transmit FIFO and a 16 byte receive FIFO.
Page 350: Operation
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 PERATION The two channels of the DUART are identical in terms of configuration and operation. They are controlled by a set of memory mapped registers, in most cases separate registers are provided for channel A and channel B (the register names are identical with either _a or _b indicating the channel);...
Page 351 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 When there is a character in the receive FIFO the duart_rx_rdy bit in the duart_status register is set, and the CPU can read it from the duart_rx_hold register. Reading the duart_rx_hold register removes the character from the FIFO. The top four bits of the status register reflect the flags (overrun error, parity error, frame error and break) associated with the character (since reading the character pops it out of the FIFO the flags should be read before the character).
Page 352: Interrupts
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 NTERRUPTS The DUART interrupts are provided as system interrupts 8 (for channel A) and 9 (for channel B). The conditions that can cause an interrupt are signalled in the interrupt status register duart_isr. This contains the channel A status in the lower four bits and the channel B status in the upper four bits.
Page 353: Loopback
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The transmit interrupt can be generated either by there being at least one free entry in the fifo (i.e. when the duart_tx_rdy status bit is set) or when the fifo is empty. The tx_irq_sel bit in the duart_mode_reg_1 is used to select between them.
Page 354: Duart Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 DUART R EGISTERS Table 197: DUART Mode Registers duart_mode_reg_1_a - 00_1006_0100 duart_mode_reg_1_b - 00_1006_0200 Bits Name Default Description duart_bits_per_char 2'b00 0: 8 1: Reserved 2: 7 3: 8 duart_parity_type 1'b0 Parity type: 0: Even/Low 1: Odd/High...
Page 355: Table 199: Duart Command Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 199: DUART Command Registers duart_cmd_a - 00_1006_0150 duart_cmd_b - 00_1006_0250 Bits Name Default Description duart_rx_en 1'b0 Enable receiver. Setting this bit at the same time as duart_rx_dis results in no change in the receiver. duart_rx_dis...
Page 356: Table 201: Duart Baud Rate Clock Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 200: DUART Status Registers (Cont.) duart_status_a - 00_1006_0120 duart_status_b - 00_1006_0220 READ ONLY Bits Name Default Description duart_frm_err 1'b0 Frame error: This flag tags a received character to indicate that this character (including parity bit) was non-zero and did not have a valid stop bit.
Page 357: Table 204: Duart Transmit Data Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 204: DUART Transmit Data Registers duart_tx_hold_a - 00_1006_0170 duart_tx_hold_b - 00_1006_0270 WRITE ONLY Bits Name Default Description tx_data Write only. Data to transmit. Writes will be ignored if the duart_tx_rdy bit is clear. 63:8 notimp 56’bx...
Page 358: Table 207: Duart Debug Access Input Port Change Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 207: DUART Debug Access Input Port Change Register duart_inport_chng_debug - 00_1006_03F0 READ ONLY, Reads have no side effects Bits Name Default Description debug These bits provide the same information as is in the duart_inport_chng register, but reads do not have side effects.
Page 359: Table 211: Duart Per Channel Output Control Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 211: DUART Per Channel Output Control Registers duart_opcr_a - 00_1006_0180 duart_opcr_b - 00_1006_0280 Bits Name Default Description reserved 1'b0 Reserved opc_sel 1'b0 Controls Cout pin for the channel. An alternative access path for the corresponding bit in the duart_opcr.
Page 360: Table 214: Duart Interrupt Status Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 214: DUART Interrupt Status Register duart_isr - 00_1006_0390 READ ONLY Bits Name Default Description duart_isr_tx_a 1'b1 Transmitter Ready duart_isr_rx_a 1'b0 Receiver Ready / FIFO Full duart_isr_brk_a 1'b0 Change in Break duart_isr_in_a 1'b0 Input Port 0,2 changes Status (input port changes for channel A)
Page 361: Table 217: Duart Interrupt Mask Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 217: DUART Interrupt Mask Register duart_imr - 00_1006_03A0 Bits Name Default Description Bits in this register must be set to cause an interrupt to be generated when the corresponding bit in the duart_isr is set.
Page 362: Table 220: Duart Output Port Set Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 220: DUART Output Port Set Register duart_set_opr - 00_1006_03B0 WRITE ONLY Bits Name Default Description Note: the output pins are the inverse of the op duart_set_op[0] op[0] 1= Set to High 0= No change duart_set_op[1]...
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Page 364: Synchronous Mode
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 YNCHRONOUS In synchronous mode, the serial data stream is accompanied by a clock and an optional gating or framing signal. There are two sub-modes, HDLC and transparent. In HDLC sub-mode, frames within the bit stream are recognized and processed according to ISO/IEC-3309 (High-level data link control (HDLC) procedures - Frame structure).
Page 365: Figure 67: Synchronous Interface Block Diagram
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Bus Interface Transmit FIFO (8 x 64 Receive FIFO (16 x 32 bit i.e. 2 cache lines) bits i.e 2 cache lines) Steering RxPack (Address TxParam TxPack RxParam Matching) TxBit (Shifter, Stuffing, RxBit (Shifter, Check TxCRC...
Page 366: Table 223: Synchronous Serial Interface Signal Names
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 NTERFACE The Line Interface controls the flow of bits between the protocol engine and the external pins. In the receive direction it assembles a bit stream and clock for the protocol engine. In the transmit direction it fetches bits from the protocol engine and formats them for the line.
Page 367: Input Line Interface
Gapped Clock: If the external device is supplying the clock on CIN_RCLKIN, it can omit clock pulses. Since the BCM1250 never receives a clock pulse this method can always be used to suppress the reception of bits. External Enable: Regardless of clock source, the RIN pin can be supplied with an externally generated enable signal.
Page 368: Input Using The Internal Sequencer
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The enable signal is level sensitive when used to enable the data. In transparent mode (see Section: “Operation in Transparent Mode” on page 349) the enable signal is used to frame the data, this can be selected as being edge (inactive to active) or level based, but only the edge based framing is likely to be useful.
Page 369: Output Line Interface
The output bits are optionally gated by means similar to the input: Gapped Clock: If the external device is supplying the clock on CTS_TCLKIN, it can omit clock pulses. Since the BCM1250 never receives a clock pulse this method can always be used to suppress the transmission of bits.
Page 370: Output Using The Internal Sequencer
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The TSTROBE pin is used as a data valid indicator when an external enable is used. The strobe_active bit in the ser_mode register sets the active level that TSTROBE will have when DOUT is valid. If the TIN enable signal is always active (or is only changed between packets) then TSTROBE will frame the packet.
Page 371: Synchronous Serial Protocol Engine
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The example in Figure 71 has the sync pulse set at time 0. The map table will be reset to entry 0 after the configured delay and then determine when DOUT is driven. In the example the delay is one (sync is sampled on the clock edge) and the data is driven for at least the first four bit times.
Page 372: Framing Parameters
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The address, control and data fields are of variable length. The lengths and formats of addresses vary among the various link-level protocols that use bit synchronous HDLC-like framing, but lengths of 0, 1 or 2 bytes are typical.
Page 373 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 In most applications, the protocol engine will compute and append a CRC. If DMA option append_CRC is not set, the user can supply a CRC as part of the DMA buffer. When the number of empty entries in the TxFIFO exceeds a configurable threshold (ser_tx_wr_thres), the DMA engine will begin to write frame data into the TxFIFO.
Page 374: Hdlc Receiver
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The transmitter can be temporarily paused (for example as the result of a flow control request) by writing the tx_pause bit in the ser_cmd register. This causes the transmitter to complete sending the current packet and then suspend operation until re-enabled.
Page 375 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Setting ser_addr_mask to all zeros disables address filtering and allows reception of all frames. Link protocols with single-byte addresses should specify masks with all zeros in the most significant byte (i.e. 16’h00ff). When the number of acceptable addresses is less than four, the remaining address registers should be filled with copies of a valid address.
Page 376: Operation In Transparent Mode
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Upon completion of the DMA transfer, any error indications forwarded through the RxFIFO are reported as status bits in the first descriptor for the corresponding frame. Table 228 lists the DMA status bits that are used by the receiver’s serial DMA channel.
Page 377: Transmitter In Transparent Mode
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Transmitter in Transparent Mode In Transparent mode, the protocol engine does not perform bit-stuffing or Flag/Abort insertion. Thus the DMA abort option is ignored. The append_CRC and append_PAD options remain available. The TIN signal is used as described in Section: “Output Line Interface”...
Page 378: Synchronous Interface Configuration
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 YNCHRONOUS NTERFACE ONFIGURATION There are four sections that must be configured before a serial channel can be used. These are: General Control, FIFO control, Protocol Engine/Line Interface Configuration and Address Filtering. In addition, the serial DMA channels must be configured.
Page 379: Synchronous Serial Interrupts
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 NTERFACE ONFIGURATION The line interface is configured in the ser_mode and ser_line_mode registers. On reset the clock source defaults to use the internal baud rate clock, ensuring that state is correctly cleared. Since changes to the line...
Page 380: Rmon Counters
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 229: Recommended Line Interface Settings for Loopback Mode 2 Field Value sync_active 1'b0 sync_delay 2'b00 strobe_active 1'b0 edge_det 1'b0 table_en 1'b1 RMON C OUNTERS The serial interface maintains some counters that are useful for gathering RMON statistics. The counters are all 16 bits wide apart from the byte counters which are 32 bits wide (but occupy two register slots).
Page 381: Table 231: Serial Mode Configuration Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 YNCHRONOUS ERIAL EGISTER UMMARY All configuration and control registers are 16 bits. Table 231: Serial Mode Configuration Register ser_mode_0 - 00_1006_0500 ser_mode_1 - 00_1006_0900 Bits Name Default Descriptions Data Format Related crc_mode 1’b0 0: CRC-CCITT. 1: CRC-32.
Page 382: Table 233: Synchronous Serial Command Register (Write-Only)
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 232: Synchronous Serial Clock Source and Line Interface Mode Register (Cont.) ser_line_mode_0 - 00_1006_0578 ser_line_mode_1 - 00_1006_0978 Bits Name Default Description rx_edge_det 1’b0 [7:6]These two bits set the interface synchronization method. 00: External Enable is used using level as frame start.
Page 383: Table 234: Serial Write Threshold Register
Number of free 64 bit entries the TxFIFO must have before it signals the DMA that space is free. This must be set to 4 for normal operation. Writing other values in this register is for Broadcom Use Only. 15:4 reserved 12’b0...
Page 384: Table 238: Serial Maximum Frame Size Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 238: Serial Maximum Frame Size Register ser_maxfrm_sz_0 - 00_1006_0510 ser_maxfrm_sz_1 - 00_1006_0910 Bits Name Default Description 15:0 size 16’hffff Maximum frame size in bytes. 63:16 notimp 48’bx Not implemented. Table 239: Serial DMA Enable Registers...
Page 385: Table 241: Serial Status Debug Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 240: Synchronous Serial Status Register (Cont.) ser_status_0 - 00_1006_0588 ser_status_1 - 00_1006_0988 READ ONLY, Read Clears Bits Name Description rx_eop_seen Set at the end of any packet transfer. It can be used during polling to determine if any packets have been transferred since the register was read (regardless of the setting of the int_pktcnt field).
Page 386: Table 243: Serial Address Mask Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 243: Serial Address Mask Register ser_addr_mask_0 - 00_1006_0518 ser_addr_mask_1 - 00_1006_0918 Bits Name Default Description 15:0 mask 16’b0 Each one bit selects the address bits in the received frame to be matched with corresponding bits in the address match registers. Bits 7:0 correspond to the first byte of the frame;...
Page 387: Table 246: Serial Rmon Counters
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 246: Serial RMON Counters ser_tx_byte_lo_0 - 00_1006_05C0 ser_tx_byte_lo_1 - 00_1006_05C0 ser_tx_byte_hi_0 - 00_1006_05C8 ser_tx_byte_hi_1 - 00_1006_05C8 ser_rx_byte_lo_0 - 00_1006_05D0 ser_rx_byte_lo_1 - 00_1006_05D0 ser_rx_byte_hi_0 - 00_1006_05D8 ser_rx_byte_hi_1 - 00_1006_05D8 ser_tx_underrun_0 - 00_1006_05E0 ser_tx_underrun_1 - 00_1006_05E0 ser_rx_overflow_0 - 00_1006_05E8 ser_rx_overflow_1 - 00_1006_05E8...
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Page 389: Section 11: Generic/Boot Bus
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 S e c t io n 11 : G e n e r ic /B oo t B us NTRODUCTION The generic bus is used to attach the boot ROM and a variety of simple peripherals. Eight regions of memory are defined, each has its own chip select line, data width and set of timing parameters.
Page 390: Configuring A Chip Select Region
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 247 shows the byte lane correspondences for the generic bus. These are discussed in more detail in the sections that follow. Table 247: Byte Lanes for the Generic Bus Mode IO_AD[31:24] IO_AD[23:16] IO_AD[15:8] IO_AD[7:0] Non Multiplex...
Page 391: Cacheable Access Blocking
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ACHEABLE CCESS LOCKING To provide protection against programming errors and prevent side effects from accidental speculative accesses through kseg0 and xkphys (see section Section: “CPU Speculative Execution” on page cacheable reads may be blocked from being driven on the generic bus. This is done by setting the blk_cache bit in the io_ext_start_addr register.
Page 392: Bus Width
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 IDTH The data width for a region is set in the io_ext_cfg register. If a region is in multiplexed address/data mode it can be set to have a data bus 8 or 16 or 32 bits wide. Regions using non-multiplexed mode must always be configured for 8 bit widths.
Page 393: Table 248: Generic Bus Timing Parameters
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 248: Generic Bus Timing Parameters Range IO_CS[0] Name Description (cycle = 10ns) Reset ale_width 1 - 7 cycles Width of the address latch enable pulse. This signal is asserted for this number of cycles to indicate the start of the cycle, the address and byte enables are output at the same time this signal asserts and remain stable after IO_ALE deasserts (i.e.
Page 394: Figure 74: Fixed Cycle Read Access
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The reference point for the IO_WR_L write strobe is the deassertion of IO_ALE, it is the responsibility of software to ensure that the assertion timing (and width in fixed cycles) places the strobe within the cycle timing.
Page 395: Fixed Cycle Write Access
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 IXED YCLE RITE CCESS clk100 ale_width idle_cycle io_ale io_ad[23:0] Address Non Muxed io_ad[31:24] Data io_ad[31:0] Address Data Muxed io_adp[3:0] Parity ale_to_cs cs_width 1 cycle io_cs_l[n] io_oe_l ale_to_wr wr_width io_wr_l io_rdy Figure 75: Fixed Cycle Write Access The fixed cycle write is the same as the fixed cycle read, except IO_OE_L remains deasserted and the ale_to_wr and wr_width parameters are used to set the assertion of the IO_WR_L signal.
Page 396: Figure 76: Acknowledge Read Access
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 CKNOWLEDGEMENT CCESS clk100 idle_cycle ale_width io_ale io_ad[23:0] Address Non Muxed Data io_ad[31:24] io_ad[31:0] Data Muxed Address Parity io_adp[3:0] 1 cycle ale_to_cs oe_to_cs io_cs_l[n] rdy_smple cs_to_oe io_oe_l io_w_lr rdy_setup cs_width io_rdy rdy_active = 0 Figure 76: Acknowledge Read Access The start of an acknowledgement access is the same as a fixed cycle, however after IO_CS_L is asserted and the cs_width interval has passed the IO_RDY line is monitored.
Page 397: Figure 77: Acknowledge Write Access
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 CKNOWLEDGEMENT RITE CCESS clk100 idle_cycle ale_width io_ale io_ad[23:0] Address Non Muxed io_ad[31:24] Data io_ad[31:0] Address Data Muxed io_adp[3:0] Parity oe_to_cs 1 cycle ale_to_cs io_cs_l[n] io_oe_l rdy_smple ale_to_wr io_wr_l cs_width rdy_setup io_rdy rdy_active = 0 Figure 77: Acknowledge Write Access The acknowledgement cycle write is the same as the read, except IO_OE_L remains deasserted and the ale_to_wr parameter is used to set the assertion of the IO_WR_L signal.
Page 398: Burst Mode
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 URST A chip select region on the generic bus can be set in a burst mode. This allows faster throughput by only doing a single address cycle at the start of the burst. However, there are some restrictions when in burst mode.
Page 399: Table 249: Burst Cycle Summary
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 249: Burst Cycle Summary Min Duration Duration (cycles) Action (cycles) ale_width ALE asserted and address driven on IO_AD ale_to_cs Rd: cs_to_oe IO_CS_L asserted, Strobe remains deasserted. Wr: ale_to_wr - On write the data becomes valid based on chip select assertion.
Page 400: Early Chip Select
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 least 1 (or more if the ready deasserts longer after the strobe). The rdy_smpl value may be used to widen the strobe if required. If the burst mode is selected with a non-multiplexed bus the address will not increment through the burst, it will remain at the start address of the burst for the entire access.
Page 401: Generic Bus Errors
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ENERIC RRORS There are five error conditions that will raise the io_bus_int interrupt. When the interrupt signal is raised the associated address, data and parity are stored and the interrupt cause recorded. The causes are: A data parity error is detected on an access to a generic bus region.
Page 402: Generic Bus Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ENERIC EGISTERS Table 251: Generic Bus Region Configuration Registers io_ext_cfg_0 - 00_1006_1000 io_ext_cfg_1 - 00_1006_1008 io_ext_cfg_2 - 00_1006_1010 io_ext_cfg_3 - 00_1006_1018 io_ext_cfg_4 - 00_1006_1020 io_ext_cfg_5 - 00_1006_1028 io_ext_cfg_6 - 00_1006_1030 io_ext_cfg_7 - 00_1006_1038 A write to any bit causes all bits to be written.
Page 403: Table 253: Generic Bus Region Base Address Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 253: Generic Bus Region Base Address Registers io_ext_start_addr_0 - 00_1006_1200 io_ext_start_addr_1 - 00_1006_1208 io_ext_start_addr_2 - 00_1006_1210 io_ext_start_addr_3 - 00_1006_1218 io_ext_start_addr_4 - 00_1006_1220 io_ext_start_addr_5 - 00_1006_1228 io_ext_start_addr_6 - 00_1006_1230 io_ext_start_addr_7 - 00_1006_1238 A write to any bit causes all bits to be written.
Page 404: Table 255: Generic Bus Region Timing 1 Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 255: Generic Bus Region Timing 1 Registers io_ext_time_cfg1_0 - 00_1006_1700 (defaults for boot ROM) io_ext_time_cfg1_1 - 00_1006_1708 io_ext_time_cfg1_2 - 00_1006_1710 io_ext_time_cfg1_3 - 00_1006_1718 io_ext_time_cfg1_4 - 00_1006_1720 io_ext_time_cfg1_5 - 00_1006_1728 io_ext_time_cfg1_6 - 00_1006_1730 io_ext_time_cfg1_7 - 00_1006_1738 A write to any bit causes all bits to be written.
Page 405 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 256: Generic Bus Interrupt Status Register (Cont.) io_interrupt_status - 00_1006_1A00 READ ONLY (Read clears interrupt) Bits Name Default Description io_cacheable_ 1’b0 When high, indicates that a cacheable access was blocked from a region that has the io_blk_cache bit set in its io_ext_start_addr register.
Page 406: Table 260: Generic Bus Error Data Register 3
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 260: Generic Bus Error Data Register 3 (Cont.) io_interrupt_data3 - 00_1006_1A28 READ ONLY Bits Name Default Description 63:16 notimp 48’bx Not implemented. Table 261: Generic Bus Error Address Register 0 io_interrupt_addr0 - 00_1006_1A30 READ ONLY...
Page 407: Table 264: Output Drive Control Register 0
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 264: Output Drive Control Register 0 (Cont.) io_drive_0 - 00_1006_1300 A write to any bit causes all bits to be written. Bits Name Default Description 13:12 reserved 2’b11 Reserved 15:14 io_drv_D 2'b01 8mA Group D drive strength control. High drive 6/8/10/12 mA. Uses Slew0.
Page 408: Table 266: Output Drive Control Register 2
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 266: Output Drive Control Register 2 io_drive_2 - 00_1006_1310 A write to any bit causes all bits to be written. Bits Name Default Description reserved 2’b11 Reserved io_drv_J 2’b01 Group J drive strength control. Low drive 2/4/6/8mA. Uses Slew0.
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Page 411: Section 12: Pcmcia Control Interface
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Sec ti o n 12 : PC MC IA C on t ro l I nte rfac e NTRODUCTION The part provides limited support for using PCMCIA memory cards attached to the generic bus. The interface allows card insertion and removal to be detected, provides and removes power from the card, and allows reading and writing of memory and attribute space on the card.
Page 412: Direct Connection Of A Memory Only Card
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 IRECT ONNECTION OF A EMORY Figure 80 shows the connections between the interface and the memory only PCMCIA slot. Chip select region 6 of the generic bus is configured in multiplexed mode and set for a 16 bit wide device. To allow hot-swap the card signals must be isolated from the generic bus.
Page 413: Table 268: Source For Pcmcia Card Enable Signals
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Since the interface inputs are 3.3V only, care must be taken to buffer inputs from the card if 5V cards need to be supported. A FET switch or translating buffer can be used to provide the voltage conversion from card...
Page 414: Table 269: Pcmcia 3.3V And 5V Vcc Power Enable Truth Table
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Software can directly control the card power using three bits in the pcmcia_cfg register, each bit corresponds to one output. These signals should be connected to an external power switch that provides the card VCC. When either CD1# or CD2# is set these bits are forced to zero and writes are ignored (i.e. software is unable to supply power if there is no card, the pwr_ctrl bit in the pcmcia_cfg register can be set to keep this behaviour when PCMCIA mode is disabled).
Page 415: Table 270: Pcmcia Vpp Power Enable Truth Table
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 269: PCMCIA 3.3V and 5V VCC Power Enable Truth Table (Cont.) Mode Input signals from Software Control Power Control Bits PCMCIA card Bits in pcmcia_cfg Card State Outputs Non-PCMCIA cd used sw set Non-PCMCIA cd used...
Page 416 • BVD2 is replaced by SPKR#, which can be used to drive a beep speaker. This would go to some other block than the BCM1250 or BCM1125/H. • BVD1 is replaced by STSCHNG# which is used to indicate the card status has changed and the card pin replacement register should be read to get the values that would otherwise be reported on the READY, WP, BVD1 or BVD2 pins.
Page 417: Using The Pcmcia Card
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 CompactFlash and CF+ cards have a similar interface to the PCMCIA cards. They also support a TrueIDE mode, which cannot be directly connected, but they are required to be able to work in the other modes so this should not be a problem.
Page 418: Example Pcmcia Timings
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 PCMCIA T XAMPLE IMINGS A flash card might have the access timings given in Table 271. Table 271: Example Flash Card AC Specs Parameter Name Min (ns) Max (ns) Read Cycle Time Address Access Time tAcca...
Page 419: Figure 81: Example Flash Card Timing Diagram
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 CLK100 tRC 220ns t_ale_width t_bus_idle IO_ALE t_cs_width t_ale_to_cs IO_CS[6] Asserted for low data byte Asserted for low data byte Asserted for high data byte Asserted for high data byte A[25:0] Address latched on ALE enabled by IO_CS[6]...
Page 420: Using The Power Outputs
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Selection of most of the parameters is straight forward. For reads the chip select width controls the cycle and must be selected to be larger than the access time. In this case it is the tAcca(max) that controls this. The chip select enables the address buffer, so the address only becomes valid after the output enable delay of the buffer (5ns in this case).
Page 421: Table 273: Pcmcia Configuration Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 PCMCIA C ONTROLLER EGISTERS The PCMCIA controller is enabled at reset time by a selection resistor on the generic address bus. The state can be read from the system configuration register. The other PCMCIA control registers are:...
Page 422: Table 274: Pcmcia Status Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 274: PCMCIA Status Register pcmcia_status - 00_1006_1A70 READ ONLY, Read clears interrupt Bits Name Default Description pcmcia_status_cd1 This bit reflects the state of the card detect 1 signal (PC_CD1_L) from the PCMCIA card. When both PC_CD1_L and PC_CD2_L are low the card is fully inserted.
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Page 424: Section 13: Gpio
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Section 13 : GPIO NTRODUCTION The part has a number of pins that are available for general use as inputs, outputs or interrupt inputs. These pins are controlled entirely by software. In addition, there are a number of pins allocated to other peripherals that may be used as general pins if the peripheral is not required.
Page 425: Table 275: Gpio Pins And Alternate Uses
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 GPIO lines can be enabled as interrupts in pairs. For each pair, both can have their interrupts disabled, both can be level interrupts, both can be edge sensitive interrupts or one can be level and the other an edge interrupt.
Page 426: Gpio Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 GPIO R EGISTERS There are eight GPIO registers. Table 276: GPIO Edge Clear Register gpio_clr_edge - 00_1006_1A80 WRITE ONLY Bits Name Default Description 15:0 edge_clr 16'h0 Writing a 1 in a bit position in this register will clear the corresponding edge detector.
Page 427: Table 280: Gpio Glitch Filter Select Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 280: GPIO Glitch Filter Select Register gpio_glitch - 00_1006_1A98 Bits Name Default Description gpio_glitch 2'h0 When high the input from the pin has a 1ms glitch filter, when low a 60 ns glitch filter. gpio_glitch 4'h0 When high the input from the pin has a 1ms glitch filter, when low a 60 ns glitch filter.
Page 428: Other Pins That Can Be Used
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 THER The part has many built in peripherals, and in any particular application it is possible that some of them are not used. Pins on some of the peripherals can be used to provide additional software controlled input, output or interrupt lines.
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Page 431: Section 14: Serial Configuration Interface
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Se ction 14: Serial Configura t ion Inte rfac e NTRODUCTION There are two serial configuration interfaces based on the SMBus. The interfaces provide hardware assistance for simple read and write of slave devices with the part as the bus master. The hardware assistance provides a subset of the SMBus version 1.1 specification published by the Smart Battery System Implementers Forum .
Page 432: Figure 83: Smbus Signaling Start, Data Transfer And Stop
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Stop A stop condition signals the end of a transaction. It consists of SDA making a transition from low to high (idle) while SCL is high (idle). Ack/Nack Start Stop from Byte of data transferred Receiver Figure 83: SMBus Signaling Start, Data Transfer and Stop A master will initiate a transfer by sending a start condition.
Page 433: Smbus Protocol
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 RANSPORT ROTOCOL ESET A system reset during an SMBus transaction can leave the bus in an unuseable state. The reset will cause the master to release the clock line and SCL will therefore go high. But many slaves do not detect the system reset, and if a slave is being read it is not permitted to change the state of the data line while the clock is high.
Page 434: Extended Protocol
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 285: Supported SMBus Transfer Types (Cont.) Transfer Type Command 1st Byte 2nd Byte Description (smb_tt) (smb_cmd) (smb_data[7:0]) (smb_data[15:8] Send Byte (000) Send a single byte to the slave. S Slave Address Wr Command Code Receive Byte (101)
Page 435: Table 286: Command/Address Options
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 The Extended protocol mode of the interface supports a much wider range of devices by allowing transactions other than those specified in SMBus. Up to seven bytes can be written to a device, and up to seven bytes read.
Page 436: Table 288: Read Data Options
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 287: Write Data Options (Cont.) smb_start [10:8] Data Format Operation No Data . . . Reserved Reserved encodings. UNPREDICTABLE operation. Table 288: Read Data Options smb_start [10:8] Data Format Operation 1 Byte S Slave Address Rd Data [7:0] .
Page 437 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 288: Read Data Options (Cont.) smb_start [10:8] Data Format Operation 6 Bytes S Slave Address Rd Command[7:0] Command[15:8] A ..Data [7:0] Data [15:8] . . . Xtra [7:0] Xtra [15:8] Reserved Reserved encoding.
Page 438 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 When the transaction finishes the busy bit will be cleared. This can either be detected by polling the smb_status register or by enabling the smb_finish interrupt. The error bit indicates that an acknowledgement was not received from the slave device at some point during the transaction. (It is important to check the data sheet for the slave device, some will always terminate a transaction by not sending an acknowledgement).
Page 439: Using Extended Protocols
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 SING XTENDED ROTOCOLS A transfer is configured by setting data values in the SMBus registers and writing the transfer type with the extend bit set to the smb_start register. This starts the operation. If the remote device fails to acknowledge when expected, then the transfer is abandoned with an error.
Page 440: Direct Access
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 IRECT CCESS The interface allows the hardware assist to be disabled giving direct ("bit-banged") access to the SDA and SCL lines. The CPU executes the whole protocol in software. This is useful for connecting to devices that deviate from the standard.
Page 441: Switching From Smbus Mode
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 EEPROMS > 16k bit (boot type = 2’b11) If the boot_type is configured as 2’b11 the part will boot from a large EEPROM (bigger than 2K bytes) accessed using the EEPROM Read protocol. The upper 4 bits of the SMBus device address are set to 4’b1010.
Page 442 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 In this example the chip select 0 timing registers are configured in one instruction bundle. The sync instructions serve to pad out the bundle and prevent the next four instructions being fetched until the stores have been issued (the SB-1 will only issue an uncacheable instruction fetch when the previous instructions have graduated).
Page 443: Smbus Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 EGISTERS The SMBus registers are mapped into the internal I/O section of the memory space. They all occupy a 64 bit wide slot, although in most cases only one or two bytes are implemented. When a register is written its entire contents must be written, writes that are smaller than the implemented width will result in the register value becoming UNPREDICTABLE.
Page 444: Table 292: Smbus Status Registers
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 292: SMBus Status Registers smb_status_0 - 00_1006_0020 smb_status_1 - 00_1006_0028 Read clears finish interrupt Bits Name Default Description smb_busy 1'b0 When high, indicates the serial interface is busy; when low, it is not busy. smb_error 1'b0 When high, indicates an error has occurred.
Page 445: Table 295: Smbus Packet Error Check Registers
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 295: SMBus Packet Error Check Registers smb_pec_0 - 00_1006_0070 smb_pec_1 - 00_1006_0078 Read returns value from previous smbus read command. Write sets value for next smbus write command. Bits Name Default Description 8’h0 This register holds the PEC information that is sent or received for a command that has the smb_pec bit set.
Page 446: Table 297: Smbus Start And Command Registers Extended Mode
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 297: SMBus Start and Command Registers Extended Mode smb_start_0 - 00_1006_0040 smb_start_1 - 00_1006_0048 Bits Name Default Description smb_addr 7'h0 The serial interface address. These 7 bits are used to form the address byte that is sent across the serial interface.
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Page 449: Section 15: Jtag And Debug
JTAG machinery can be used while COLDRES_L is asserted. If testing is to be done using the JTAG interface with the BCM1250 held in reset then RESET_L should be used to keep the system in reset while allowing the JTAG port to be active. The standard EJTAG connector allows the probe to control RESET_L.
Page 450: Figure 84: Jtag Tap State Machine
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Test-Logic-Reset Run-Test-Idle Select-DR-Scan Select-IR-Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR Figure 84: JTAG TAP State Machine B r oadco m C orp or ati on Page Section 15: JTAG and Debug...
Page 451: Table 299: Jtag Instructions
BYPASS, SAMPLE/PRELOAD, and EXTEST instructions are implemented, along with the optional IDCODE, INTEST and CLAMP instructions. 25 additional BCM1250 specific instructions have been implemented. The instruction register is scanned in and out LSB first. The value scanned out of the instruction register has a 1 in the LSB and zeros in all other bits.
Page 452: Bypass Instruction
0 0 1 0 1 0 1 0 0 0 0 1 The version number is 4’h1 for prototype BCM1250, 4’h2-4’h8 or 4’hb for initial production BCM1250 and 4’h9 for later production BCM1250 (stepping C0).
Page 453: Impcode Instruction
This instruction selects the Implementation register for output, which is always 32 bits. The impcode for the BCM1250 and BCM1125/H is 32’h21404001 indicating EJTAG 2.5, R4k style CP0, DINT supported, ASID size is 8 bits, no MIPS16 support, no EJTAG DMA, MIPS64 support. This code is defined by revision 2.5 of the MIPS EJTAG spec.
Page 454: Normalboot Instruction
CPU1 to CPU0 to TDO. These scan chains are for Broadcom Use Only. Scanning inappropriate values in to the chains can put the BCM1250 in an UNDEFINED state that requires both a system and a JTAG reset to clear.
Page 455: Table 302: System Control Scan Chain
Configuration bit for IO_AD[1]. Indicates source for IO_CLK100. This must not be changed while the BCM1250 is operating. ldt_minrstcnt Configuration bit for IO_AD[2]. Broadcom Use Only. This must be zero for normal operation. ldt_bypass_pll Configuration bit for IO_AD[3]. Broadcom Use Only. This must be zero for normal operation.
Page 456 When set CPU 0 will be held in reset. cpu_reset_1 1'b1 When set CPU 1 will be held in reset. This bit is set on a BCM1250 reset, causing the processor to remain in reset until released under software control. unicpu0 1'b0 Set to indicate uniprocessor using physical processor 0.
Page 457: Trace Instruction
Broadcom-soft-reset bit is set, following the reset the BCM1250 will behave as a uniprocessor. This can be used to disable one of the processors, it will not be clocked and will enter a low power state.
Page 458: Tracectrl And Tracecurcnt Instructions
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 TRACECTRL and TRACECURCNT Instructions The trace control registers are selected for both scan in and out using the TRACECTRL instruction. The registers are connected between TDI and TDO and are scanned out LSB first. The registers are scanned out...
Page 459: Processmon Instruction
9:8 of the data register. When this instruction is selected the counter only counts while DEBUG_L pin is asserted. Ring oscillators will run at less than 1 GHz. This is for Broadcom Use Only. Table 306: Ring Oscillator Scan Chain...
Page 460: Figure 85: Jtag Boundary Scan Register Block
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Figure 85 shows an example of the boundary scan register and the shadow register for most of the pins on the part. All the pins apart from HyperTransport use this input/output pin building block. It consists of three BC_1 scan cells, one for the output, one for the output enable and one for the input.
Page 461: Figure 86: Jtag Hypertransport Output Boundary Scan Block
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 To use the boundary scan and EXTEST to test board connectivity the following steps should be performed: The TAP controllers of both parts under test are set to the EXTEST instruction. The desired pattern on the output pins is shifted into the BSR shadow register.
Page 462: Figure 87: Jtag Hypertransport Input Boundary Scan Block
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 The HyperTransport input block, shown in Figure 87, is similar. It uses two BC_1 cells to monitor the two pins. However, these will always be inverses when a correct differential signal is received. The outputs of the BC_1 cells can be used to drive the single data rate version of the data into the part simplifying INTEST vector injection.
Page 463: Processor And Probe Access
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 ROCESSOR AND ROBE CCESS The JTAG probe can act as both a master and a slave on the ZBbus. As a master, the probe can initiate any bus transaction. As a slave, the probe responds to accesses in the EJTAG memory range 00_1000_0000 to 00_1001_FFFF.
Page 464: Figure 88: Example Jtag Probe Flowchart
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Need JTAG to ZBbus? Scan In/Out EJTAG Control Register With MaSl = 1 Scan Out EJTAG Control Register PrAcc Bit = 1? Scan Out EJTAG Control Register PrAcc Bit = 1? PrAcc Bit = 1 Service...
Page 465: Processor Accesses To The Jtag Space
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 JTAG S ROCESSOR CCESSES TO THE PACE When the JTAG probe is configured for slave accesses, an access to the JTAG range (00_1000_0000 to 00_1001_FFFF) is responded to by the debugger. If the CPU is set to use the Alternate Debug Vector then a debug exception will cause it to fetch instructions from 00_1000_0480.
Page 466: Address Register
BCM1250/BCM1125/BCM1125H User Manual 10/21/02 DDRESS EGISTER The Address Register is 77 bits long and contains the address bits, byte enables, bus command and cache attributes. To maintain coherency the cache attributes must be set correctly for the address so snoop...
Page 467: Ejtag Control Register
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 EJTAG C ONTROL EGISTER This is a 12 bit register to control the various operations of the debug support modules.This register is selected by shifting in the CONTROL instruction. Bits in the EJTAG Control Register can be set/cleared by shifting in data;...
Page 468 When clear CPU transactions will be accepted if ProbEn is set. 0: CPU accesses accepted. 1: Probe can initiate a bus transaction. ClkStop Clock stop flag. This bit is for Broadcom Use Only. B r oadco m C orp or ati on Page Section 15: JTAG and Debug...
Page 469: Differences From Ejtag 2.5 (Feb. 22, 2000) Specification
IFFERENCES FROM PECIFICATION The BCM1250 has some differences from the EJTAG 2.5 due to support for the dual processor configuration and system level debug access. A summary, with reference to the section numbers in the EJTAG 2.5 (Feb. 22, 2000) specification: 2.2.2...
Page 470 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 5.5.4 The address register is 77 bits (contains ZBbus address + cmd) 5.5.5 Rocc - Not implemented Psz - Not implemented, size in address register Doze - Not implemented Halt - Not implemented PerRst - Use System Config register for resets...
Page 471 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 This Page is left blank for notes B r oadco m C orp or ati on Document 1250_1125-UM100CB-R Section 15: JTAG and Debug Page...
Page 472 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 This Page is left blank for notes B r oadco m C orp or ati on Page Section 15: JTAG and Debug Document 1250_1125-UM100CB-R...
Page 473: Table 311: Internal Register Addresses By Function
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 S e c t io n 1 6 : R e f e r e n c e NTERNAL EGISTER DDRESSES BY UNCTION This section lists the registers and address assignments, per ZBbus agent. In the electronic version of the document the Table/Page column provides a hyperlink to the table that defines the register.
Page 474 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page mc_cs_attr_0 85/143 Channel 0 CS[3:0]attribute. 00_1005_1380 mc_test_data_0 86/144 Channel 0 ECC error set data bits. 00_1005_1400 mc_test_ecc_0 87/144 Channel 0 ECC error set ecc bits.
Page 475 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page mac_rx_bytes_0 167/289 RMON total received bytes. 00_1006_4080 mac_rx_mcast_0 167/289 RMON total received multicast packets. 00_1006_4088 mac_rx_bcast_0 167/289 RMON total received broadcast packets. 00_1006_4090...
Page 476 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page mac_addr5_0 187/314 Address filter exact match. 00_1006_42A8 mac_addr6_0 187/314 Address filter exact match. 00_1006_42B0 mac_addr7_0 187/314 Address filter exact match. 00_1006_42B8 mac_chup0_0 193/318 Receive DMA channel select MSB.
Page 477 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page Serial Ports duart_mode_reg_1a 197/327 Mode register 1 port A MR1A. 00_1006_0100 duart_mode_reg_2a 198/327 Mode register 2 port A MR2A. 00_1006_0110 duart_status_a 200/328 Status register port A (Read Only).
Page 478 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page duart_inport_chng_b 209/331 Input port change register for channel B (Read Only, read 00_1006_03E0 clears channel B change state) duart_inport_chng_debug 207/331 Alias of input port change register with no read side 00_1006_03F0 effects.
Page 479 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page ser_tx_byte_hi_0 246/360 Serial interface transmit byte count (high 16 bits). 00_1006_05C8 ser_rx_byte_lo_0 246/360 Serial interface receive byte count (low 16 bits). 00_1006_05D0 ser_rx_byte_hi_0 246/360 Serial interface receive byte count (high 16 bits).
Page 480 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page ser_tx_table14_0 245/359 Sequence table. 00_1006_0770 ser_tx_table15_0 245/359 Sequence table. 00_1006_0778 dma_config0_ser_1_rx 91/163 Receive DMA control register. 00_1006_0800 dma_config1_ser_1_rx 92/164 Receive DMA control register.
Page 481 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page ser_rx_byte_lo_1 246/360 Serial interface receive byte count (low 16 bits). 00_1006_09D0 ser_rx_byte_hi_1 246/360 Serial interface receive byte count (high 16 bits). 00_1006_09D8 ser_tx_underrun_1 246/360 Serial interface transmit underrun count.
Page 482 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page ser_tx_table15_1 245/359 Sequence table. 00_1006_0B78 Generic Bus io_ext_cfg_0 251/375 cs0 interface configuration. 00_1006_1000 io_ext_cfg_1 251/375 cs1 interface configuration. 00_1006_1008 io_ext_cfg_2 251/375 cs2 interface configuration.
Page 483 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page io_ext_time_cfg0_6 254/376 cs6 Timing parameter configuration 0. 00_1006_1630 io_ext_time_cfg0_7 254/376 cs7 Timing parameter configuration 0. 00_1006_1638 io_ext_time_cfg1_0 255/377 cs0 Timing parameter configuration 1.
Page 484 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page Output Drive Control io_drive_0 264/379 3.3V output drive strength and slew rate control registers. 00_1006_1300 Section: “Drive Strength Control” on page 374. io_drive_1...
Page 485 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page general_timer_init_cnt_3 26/60 General timer initial count. 00_1002_0178 general_timer_cnt_2 27/60 General timer current count (Read Only). 00_1002_0180 general_timer_cnt_3 27/60 General timer current count (Read Only).
Page 486 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page SCD: Interrupt Mapper interrupt_diag_0 21/52 Force interrupt diagnostic register. 00_1002_0010 interrupt_mask_0 21/52 Interrupt mask. 00_1002_0028 interrupt_source_status_0 21/52 Status of system interrupt sources (Read Only).
Page 487 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page interrupt_map11_0 18/47 Source to IRQ map register. 00_1002_0258 interrupt_map12_0 18/47 Source to IRQ map register 00_1002_0260 interrupt_map13_0 18/47 Source to IRQ map register.
Page 488 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page interrupt_map48_0 18/47 Source to IRQ map register. 00_1002_0380 interrupt_map49_0 18/47 Source to IRQ map register. 00_1002_0388 interrupt_map50_0 18/47 Source to IRQ map register.
Page 489 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page SCD: Debug Controller jtag_space JTAG serviced debug space 1000_0000-1001_ffff. 00_1000_0000 SCD: Trace Buffer trace_cfg 48/76 Trace configuration. 00_1002_0a00 trace_read 50/79 Trace buffer read register (Read Only).
Page 490 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 311: Internal Register Addresses by Function (Cont.) Table/ Address Name Description Page dm_dscr_addr_2 117/185 Data Mover channel 2 current address (Read Only). 00_1002_0b50 dm_debug_dscr_base_2 115/184 Debug alias for channel 2 ring base address (Read Only, 00_1002_0b58 no side effects).
Page 491: Table 312: Internal Registers Ordered By Address
User Manual BCM1250/BCM1125/BCM1125H 10/21/02 BCM1250/BCM1125/H I NTERNAL EGISTERS RDERED BY DDRESS Table 312: Internal Registers Ordered by Address Table/ Name Address Description Page jtag_space JTAG serviced debug space 1000_0000-1001_ffff. 00_1000_0000 system_revision 14/43 System Id and revision (Read Only). 00_1002_0000 system_cfg 15/43 System configuration register.
Page 492 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page interrupt_status5_0 21/52 Status of mapped interrupt sources (Read Only). 00_1002_0128 interrupt_status6_0 21/52 Status of mapped interrupt sources (Read Only). 00_1002_0130 interrupt_status7_0 21/52 Status of mapped interrupt sources (Read Only).
Page 493 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page interrupt_map24_0 18/47 Source to IRQ map register. 00_1002_02c0 interrupt_map25_0 18/47 Source to IRQ map register. 00_1002_02c8 interrupt_map26_0 18/47 Source to IRQ map register.
Page 494 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page interrupt_map61_0 18/47 Source to IRQ map register. 00_1002_03e8 interrupt_map62_0 18/47 Source to IRQ map register. 00_1002_03f0 interrupt_map63_0 18/47 Source to IRQ map register.
Page 495 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page trace_event_3 46/72 Trace event selector. 00_1002_0a38 trace_sequence_0 47/74 Trace sequence and action. 00_1002_0a40 trace_sequence_1 47/74 Trace sequence and action. 00_1002_0a48 trace_sequence_2 47/74 Trace sequence and action.
Page 496 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page ctcp_def_1 119/186 CRC and checksum definition register. 00_1002_0b98 dm_partial_0 120/186 CRC/Checksum partial result register. 00_1002_0ba0 dm_partial_1 120/186 CRC/Checksum partial result register. 00_1002_0ba8 dm_partial_2 120/186 CRC/Checksum partial result register.
Page 497 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page mc_cs0_col_0 83/142 Channel 0 CS0 column address bits. 00_1005_1220 mc_cs0_ba_0 84/143 Channel 0 CS0 bank select. 00_1005_1240 mc_cs1_row_0 82/142 Channel 0 CS1 row address bits.
Page 498 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page duart_full_ctl_a 202/329 Full control port A. 00_1006_0140 duart_cmd_a 199/328 Command register port A. 00_1006_0150 duart_rx_hold_reg_a 203/329 RX holding register port A (Read Only, read pops 00_1006_0160 character from FIFO).
Page 499 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page dma_dscr_base_ser_0_rx 93/166 Receive DMA descriptor base address. 00_1006_0410 dma_dscr_cnt_ser_0_rx 95/166 Receive DMA descriptor count . 00_1006_0418 dma_cur_dscr_a_ser_0_rx 96/167 Receive DMA current descriptor A (Read Only).
Page 500 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page ser_rx_errors_0 246/360 Serial interface receive error packet count. 00_1006_05F0 ser_rx_badaddr_0 246/360 Serial interface receive address mismatch count. 00_1006_05F8 ser_rx_table0_0 245/359 Sequence table. 00_1006_0600...
Page 501 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page dma_dscr_count_ser_1_rx 95/166 Receive DMA descriptor count. 00_1006_0818 dma_cur_dscr_a_ser_1_rx 96/167 Receive DMA current descriptor A (Read Only). 00_1006_0820 dma_cur_dscr_b_ser_1_rx 97/167 Receive DMA current descriptor B (Read Only).
Page 502 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page ser_rx_badaddr_1 246/360 Serial interface receive address mismatch count. 00_1006_09F8 ser_rx_table0_1 245/359 Sequence table. 00_1006_0A00 ser_rx_table1_1 245/359 Sequence table. 00_1006_0A08 ser_rx_table2_1 245/359 Sequence table.
Page 503 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page io_ext_cfg_4 251/375 cs4 interface configuration. 00_1006_1020 io_ext_cfg_5 251/375 cs5 interface configuration. 00_1006_1028 io_ext_cfg_6 251/375 cs6 interface configuration. 00_1006_1030 io_ext_cfg_7 251/375 cs7 interface configuration.
Page 504 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page io_ext_time_cfg0_7 254/376 cs7 Timing parameter configuration 0. 00_1006_1638 io_ext_time_cfg1_0 255/377 cs0 Timing parameter configuration 1. 00_1006_1700 io_ext_time_cfg1_1 255/377 cs1 Timing parameter configuration 1.
Page 505 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page mac_tx_good_0 167/289 RMON total sucessfully transmitted packets. 00_1006_4040 mac_tx_runt_0 167/289 RMON total runt packets transmitted. 00_1006_4048 mac_tx_oversize_0 167/289 RMON total oversize packets transmitted.
Page 506 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page mac_addr2_0 187/314 Address filter exact match. 00_1006_4290 mac_addr3_0 187/314 Address filter exact match. 00_1006_4298 mac_addr4_0 187/314 Address filter exact match. 00_1006_42A0 mac_addr5_0 187/314 Address filter exact match.
Page 507 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Table 312: Internal Registers Ordered by Address (Cont.) Table/ Address Name Description Page Type 00 PCI header 127/236 Configuration space bus=0,dev=0. 00_FE00_0000 00_FE00_00FF Type 01 PCI header 140/245 Configuration space bus=0,dev=1. 00_FE00_0800 00_FE00_08FF B r oadco m C orp or ati on...
Page 508 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 B r oadco m C orp or ati on Page Section 16: Reference Document 1250_1125-UM100CB-R...
Page 509 Cause Accesses from the HyperTransport to the BCM1250 CF+ cards Accesses from the PCI to the BCM1250 Channel Select Accessing the BCM1250 from an BCM1250 on a Double Hosted checksum Chain Checksum Generation Accessing the BCM1250 from HyperTransport Devices Chip Select...
Page 510 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 dm_dscr_base_1 duart_out_port 324, 335 dm_dscr_base_2 duart_rx_hold 326, 329 dm_dscr_base_3 duart_set_opr 324, 335 dm_dscr_count 185 duart_status 323, 328 dm_partial 186 duart_tx_hold 323, 330 ASIC mode buffer ECC Diagnostic Management Accesses (ECC diag bits nonzero) buffers bytes before offset overwritten...
Page 511 User Manual BCM1250/BCM1125/BCM1125H 10/21/02 Example Startup Code to clear the L2 Cache Explicit Descriptor Interrupts Error Control Register 253 Error Status Register 254 expansion space Feature Control function FIFO Configuration generating interrupt messages Fixed Cycle Write Access I/O space Flow Control...
Page 512 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 io_interrupt_addr0 mac_status1_2 io_interrupt_addr1 mac_thrsh_cfg 272, 275, 294, 307 io_interrupt_data0 378 mac_txd_ctl 274, 306 io_interrupt_data1 378 mac_type_cfg 316 io_interrupt_data2 378 mac_vlantag 152, 164, 274, 285, 310 io_interrupt_data3 378 MACs io_interrupt_parity 379 mailbox 48, io_interrupt_status 18, 364, 374, 377...
Page 513 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 CAS time check PCMCIA Closed attribute memory Hint Based status signals Open PCMCIA Power Control Pins Pause Frame 279, pcmcia_cfg 386, 387, 390, 393, 394 Pause frame pcmcia_status 395 pause frame 152, 164, 168, 267, 271,...
Page 514 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 ser_rx_table 359 ser_status 157, 341, 343, 346, 349, 357 TCP 178, ser_status_debug 358 TCP checksum ser_tx_rd_thres 346, 356 Terminology ser_tx_table 359 The GPIO Pins ser_tx_wr_thres 346, 356 Timer Registers ser_usr0_addr 359 Timer Special Cases Serial Configuration Interface...
Page 515 BCM1250/BCM1125/BCM1125H User Manual 10/21/02 B roa dcom Co rpo rat ion Page Index Document 1250_1125-UM100CB-R...
Page 516 Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

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