Table 255: Generic Bus Region Timing 1 Registers; Table 256: Generic Bus Interrupt Status Register - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
io_ext_time_cfg1_0 - 00_1006_1700 (defaults for boot ROM)
Bits Name
2:0 io_ale_to_write
3 rdy_sync
7:4 io_write_width
11:8 io_idle_cycle
13:12 io_oe_to_cs
15:14 io_cs_to_oe
63:16 notimp
io_interrupt_status - 00_1006_1A00 READ ONLY (Read clears interrupt)
Bits Name
7:0 io_cs_err_int
8 reserved
9 io_rd_par_int
10 io_timeout_int
11 io_ill_addr_int
12 io_mult_cs_int
Page 376 Section 11: Generic/Boot Bus

Table 255: Generic Bus Region Timing 1 Registers

io_ext_time_cfg1_1 - 00_1006_1708
io_ext_time_cfg1_2 - 00_1006_1710
io_ext_time_cfg1_3 - 00_1006_1718
io_ext_time_cfg1_4 - 00_1006_1720
io_ext_time_cfg1_5 - 00_1006_1728
io_ext_time_cfg1_6 - 00_1006_1730
io_ext_time_cfg1_7 - 00_1006_1738
A write to any bit causes all bits to be written.
Default
_0 3'h7 Assertion of write strobe after the deassertion of ALE.
3'h1
1'b0 If this bit is clear the IO_RDY input is an asynchronous input and will be internally
synchronized so there is no need for the peripheral to meet the setup and hold
specification on the signal. If this bit is set the synchronizer is bypassed, so the
acknowledgement is detected earlier by the generic bus state machine, but the
peripheral must meet the setup and hold time specification.
_0 4'h7 Width of the write strobe
4'h1
_0 4'h6 Number of idle cycles between back_to_back operations.
4'h1
2'h0 Number of cycles IO_OE_L deasserts before IO_CS_L deasserts. In
acknowledgement mode this parameter is also the number of cycles between
IO_WR_L deasserts and IO_CS_L deasserts.
2'h0 Number of cycles between IO_CS_L assertion and IO_OE_L assertion. This
parameter must be less than io_cs_width.
48'bx Not implemented.

Table 256: Generic Bus Interrupt Status Register

Default
8'h0 Indicates which of the 8 chip select regions have an error resulting in an interrupt. This
field is only valid when one or more of bits [9], [10], [13], or [14] are set.
1'b0 Not used, reads as zero.
1'b0 When high, indicates parity error on read data from a parity enabled device. The
address of the 32 bit word accessed will be put in the address log, the data in the
appropriate part of the data log, and the parity in the appropriate part of the parity log.
1'b0 When high, indicates timeout has occurred on one of the IO blocks. The address that
was being accessed is put in the address log.
1'b0 When high, indicates an address referenced did not match any region. The address
that was being accessed is put in the address log.
1'b0 When high, indicates multiple chip selects selected based on the address accessed.
The address that was being accessed is put in the address log.
B r oadco m C orp or ati on
Description
Description
Document
User Manual
10/21/02
1250_1125-UM100CB-R