Broadcom BCM1250 User Manual page 165

User Manual
10/21/02
Table 73: Memory Channel Configuration Register on BCM1125/H
Bits Name Default
52 iob1_priority 1'b1
55:53 reserved 3'b0
59:56 cs_mode 4'h0
60 ecc_disable 1'b0
61 berr_disable 1'b0
62 force_seq 1'b0
63 reserved 1'b0
Document 1250_1125-UM100CB-R
mc_config_0 - 00_1005_1100
mc_config_1 - 00_1005_2100
Description
mc_config_1: If this bit is set reads from I/O bridge 1 will be given high priority (to
reduce their latency). If clear all requests have the same priority.
mc_config_0: Reserved.
Reserved
mc_config_1: Chip Selection mode
0000: msb-CS mode: CS[3:0]are determined by the corresponding CS start/end+1
address registers.
1111: Interleaved-CS mode: the values of start/end+1 addresses of CS[3:0] are all
same in this mode, CS[3:0] are decoded by the two bits in the interleaved CS
position register.
1100: Mixed-CS mode: CS[1] and CS[0] are not interleaved and determined by the
corresponding start/end+1 addresses. The interleaving occurs between CS3
and CS2, determined by one bit of the interleaved CS position register. The
values of the CS[3:2] start/end+1 addresses are the same.
0110: Mixed-CS mode: CS[3] and CS[0] are not interleaved and determined by the
corresponding start/end+1 addresses.Tthe interleaving occurs between CS2
and CS1, determined by one bit of the interleaved CS position register. The
values of the CS[2:1] start/end+1 addresses are the same.
0011: Mixed-CS mode: CS[3] and CS[2] are not interleaved and determined by the
corresponding start/end+1 addresses. The interleaving occurs between CS1
and CS0, determined by one bit of the interleaved CS position register. The
values of the CS[1:0] start/end+1 addresses are the same.
mc_config_0: Reserved.
mc_config_1: ECC disable. If this bit is set ECC checking will not be performed
and data will never be reported to have an error.
mc_config_0: Reserved.
mc_config_1: Bus error disable. This bit sets the behavior when a read is done to
an address that does not match any chip select range.
0: Generate a bus error data return
1: Generate a valid data return containing UNPREDICTABLE data.
mc_config_0: Reserved.
mc_config_1: Force Sequential. If this bit is set requests will be issued to memory
in the same order their A-phase happens on the ZBbus.
mc_config_0: Reserved.
Reserved
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
(Cont.)
Section 6: DRAM Page 137